70 results on '"HOLT, J"'
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2. A 7nm CMOS technology platform for mobile and high performance compute application
3. Characterization of atomic layer deposited low-k spacer for FDSOI high-k metal gate transistor
4. Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges
5. Hydrogenation of Si from SiN_x: H films: how much hydrogen is really in the Si?
6. Semi-formal and formal interface specification for system of systems architecture
7. 22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
8. PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology
9. Verification coverage of embedded multicore applications
10. Radar subsurface sounding over the putative frozen sea in Cerberus Palus, Mars
11. To upgrade or not to upgrade? Catamount vs. Cray Linux Environment
12. High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
13. Hole Transport in Nanoscale p-type MOSFET SOI Devices with High Strain
14. Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current
15. High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology
16. (110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering
17. Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices
18. High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
19. Testing Safety Critical Systems with SysML/UML.
20. Context-based Systems Engineering.
21. High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering
22. MCC: A runtime verification tool for MCAPI user applications.
23. System-level Performance Verification of Multicore Systems-on-Chip.
24. Early Models for System-Level Power Estimation.
25. Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices.
26. Workload Slicing for Characterizing New Features in High Performance Microprocessors.
27. Selective epitaxial channel ground plane thin SOI CMOS devices.
28. Design of high performance PFETs with strained si channel and laser anneal.
29. Enabling iterative software architecture derivation using early non-functional property evaluation.
30. Providing early feedback in the development cycle through automated application of model checking to software architectures.
31. Calibration Of Bonanza Creek, Alaska, Sar Imagery Using Along-track Calibration Targets.
32. Polarization Signatures Of Frozen And Thawed Forests Of Varying Biomass.
33. Timing analysis in OO system life-cycles.
34. Improving the PIM routing protocol with adaptive switching mechanism between its two sparse sub-modes.
35. Novel rapid-thermal-processing for CIS thin-film solar cells.
36. An innovative routing protocol evaluation tool.
37. Polarization signatures of frozen and thawed forests of varying environmental state.
38. The combined use of satellite differential Doppler and ground-based measurements for ionospheric studies.
39. Flow Through Collapsible Tubes and Through in Situ Veins.
40. A Winchester data path and servo signal processor family
41. A two-quadrant analog multiplier integrated circuit
42. Dual stress liner enhancement in hybrid orientation technology
43. Measurement of Tevatron extraction parameters and comparison of model to measurements
44. Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates
45. Beam-based optical tuning of the Final Focus Test Beam
46. Calibration Of Bonanza Creek, Alaska, Sar Imagery Using Along-track Calibration Targets
47. Polarization Signatures Of Frozen And Thawed Forests Of Varying Biomass
48. High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
49. Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain.
50. FinFET resistance mitigation through design and process optimization.
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