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A high accuracy positioning service named PAS, based on nationwide RTK-GPS and FKP method, has been realized in Japan, and commercially operated since September 2003. Cm-level accuracy is obtained and uniformity in the service area is also validated. Application to a human navigation prototype system is also shown with a real image on a cellular telephone, and will be linked to the PAS system to serve as a location base service in the near future

Cm-level high accuracy real-time GPS positioning system is realized nation wide in Japan based on networked Real Time Kinematics GPS (RTK-GPS), and has been commercially operated by Mitsubishi Electric Co. named PAStrade, Positioning Augmentation Services, since September 2003. Also we have recently devised more convenient method at submeter or decimeter accuracy using low cost and compact code-ranging GPS receiver utilizing correction data fed from PAS system. Both of these methods will reduce time and cost significantly to produce precise satellite imagery based on Ground Control Point (GCP), as well as to update maps in geo-centric coordinate, which is necessary to use satellite imagery operationally with GPS

Considering the development of an efficient coding technique for high-fidelity compression of very high resolution images, the authors first compare three different scalar quantization schemes and improved permutation codes from the aspect of quantization performance for a memory-less probability distribution that well approximates the real statistical properties of high frequency sub-band signals, and demonstrate that at low coding rates the improved permutation codes algorithm is the most suitable quantization scheme. Furthermore, the authors develop a rate-adaptive quantization technique that chooses the proper quantization scheme from among different types of quantization schemes according to the number of bits allocated to each subblock, and apply it to the high-fidelity encoding of sub-band signals. The results of simulations conducted on very high resolution images demonstrate that the proposed rate-adaptive quantization technique is very useful as a means for quantizing sub-band signals of very high resolution images. >

For the improvement of the transparency of CdS window layers produced by the printing and sintering method, a new substrate structure is proposed and examined. It is found that insertion of a TiO/sub 2/ and SiO/sub 2/ mixed layer between the glass substrate and CdS window layer diminishes the pores in CdS window layer. This is due to the good wettability between the CdS layer and TiO/sub 2/-SiO/sub 2/. A CdTe solar cell with this CdS layer (2.8/spl times/10 cm/sup 2/) has a high J/sub sc/ of 21 mA/cm/sup 2/. Another trial to achieve high package factor (the ratio of active-area/total-area) and high area productivity have also been carried out. By developing a wide-width writing method laser scribed CdTe/C double layer, the package factor increases from 85% to 90% and an efficiency of 8.7% is obtained in a 30/spl times/40 cm/sup 2/ submodule. >

By reduction of the operating current density due to a long cavity length of 900 /spl mu/m, reliable 5,000-hour operation of 680-nm window lasers has been realized under the conditions of 70 mW at 60/spl deg/C and 100 mW at 40/spl deg/C for the first time.

The DFB-LD with a width-tapered waveguide lens is fabricated and narrow beam divergence property is realized. Excellent light output-current (L-l) characteristics in wide-temperature range and error-floor-free transmission at 622 Mbps-40 km are also confirmed. It is promising for the surface-mountable DFB-LD modules.

We have investigated the selective MOCVD re-growth of InP around mesa-stripes along [11¯0] direction formed with reactive ion etching by the addition of HCl gas during MOCVD growth. It is shown that the large overgrowth on the SiO 2 mask in the conventional growth condition is remarkably reduced by the addition of the HCl gas. The mechanism of this effect is analyzed experimentally. It is found that the growth rate on (110) plane (mesa side wall) decreases more remarkably than that on the (001) plane (mesa base) with increasing HCl flow rate. Therefore the growth rate on the side wall can be effectively reduced by the addition of adequate amount of HCl. The reduction of the growth rate on the (110) plane suppress the formation of (111)A plane, which is the cause of the large overgrowth near the mask edge of the mesa stripes. Using these results, we have successfully achieved planar embedded re-growth of InP around dry-etched mesa along [11¯0] direction. This technique is very useful in the application of selective MOCVD growth to the photonic integrated circuits

It has been noted that the soft error rate of the partially depleted SOI (PD-SOI) SRAM is not improved as compared with bulk CMOS SRAMs due to floating body effects through simulation (Tosaka et al. 1995). There has been no soft error data reported in the papers on SOI SRAMs, except for those used for space applications. In high-density PD-SOI SRAMs, a body contact is essential to reduce soft error rates. It has been proposed that a thin well layer left between the isolation and the buried oxide can provide a convenient body contact layer that has no area penalty and is compatible with bulk CMOS (Chen et al. 1996). However, soft error data and the required body contact resistance needed to suppress the floating body effect has not been clear. Thus, we have fabricated 288-kbit SRAM test chips with 0.35 /spl mu/m CMOS technology and confirmed that the soft error rate can be improved. We also estimated the body contact resistance required for soft error improvement through device simulation.

We demonstrate a new approach to realize the graded grating, which is effective to improve the modulation characteristics of DFB laser diodes (LDs) for analog optical transmission, by using selective-area-growth (SAG) technique. Ideal parabolic thickness profile and the thickness enhancement ratio as high as 4.6 in the grating layer have been realized by optimizing the mask shape using the simulation technique for SAG. We have also successfully realized the high light-current linearity in 1.3 /spl mu/m DFB-LDs with graded grating for the first time. It has been shown that the LDs have excellent distortion characteristics.

We have fabricated a distributed-feedback laser diode (DFB-LD) with monolithically integrated electroabsorption modulator (EAM), which has small chirp characteristics (effective /spl alpha/ parameter =0.2). 2.5 Gbps-700 km penalty-free transmission without any intentional pre-biasing or self phase modulation effect is successfully demonstrated using the EAM-LD.

Beryllium (Be) has been investigated as p-type dopant for InGaAs layers grown using bismethylcyclopentadienyl-beryllium ((MeCp)/sub 2/Be) by low-pressure metalorganic chemical vapor deposition. It is found that hole concentration is in proportion to the (MeCp)/sub 2/Be flow rate, which results in excellent doping controllability. Moreover, the doping efficiency of (MeCp)/sub 2/Be is one order of magnitude higher than that of diethylzinc (DEZn). InGaAs increases with increasing growth temperature in the temperature range from 570 to 625/spl deg/C. Heavily Be-doped InGaAs layers with specular surface morphology have been attained with a hole concentration in excess of 10/sup 19/ cm/sup -3/ by optimization of growth condition. (MeCp)/sub 2/Be is promising precursor as p-type dopant source for optoelectronic devices.

High bandwidth has become one of the most important features in high-speed embedded cache memories in recent superscalar RISC processors. This 285 MHz, two-port 16kB (512/spl times/256) cache macro has a 2 ns access time. In this cache, the data of memory cells are sent to a read bus in the first half of the cycle time, and write data from a write bus are written to memory cells in the second half of the cycle time. This performance is achieved because of a hierarchical bit-line architecture that uses double global bit-line pairs (WGB), and a high-speed timing-free sense amplifier that shortens access time.

From 1995, Matsushita Battery Co., Ltd has been developing a low cost and efficient technologies to fabricate a thin-film CdS/CdTe solar cell. Earlier, the authors reported a conversion efficiency of 10.5% for a middle size sub-module (1376 cm/sup 2/) [1] and 16.0%, efficiency for 1 cm/sup 2/ cells. They report here a highly efficient large area CdS/CdTe solar cell (11.0%, 5413 cm/sup 2/) sub-module. The key technologies to fabricate the high efficiency modules are the suppression of the diffusion of F ion into CdS layer, CdTe stoichiometry, the film thickness and uniformity of all the constituent layers such as SnO/sub 2/:F, CdS and CdTe prepared under atmospheric pressure conditions.

Recent advances in ultra-thin silicon-on-insulator (SOI) technology have made partially depleted (PD)-SOI-CMOS a promising candidate for use in high-speed circuits. However, some breakthroughs must still be made, the most important of which would be understanding and control of hysteretic behavior. Some hysteretic characteristics have been analyzed, and some methods to suppress this behavior have been proposed (Assaderaghi et al., 1994; Houston et al., 1998; Maeda et al., 1998; Wei et al., 1998; Pelella et al., 1999). However, the operation-period dependent circuit-delay is not sufficiently understood. In this paper, closed form analysis was used to analyze the operation-period-dependent circuit delay, and the results were confirmed with circuit simulators.

Cadmium Telluride is the most promising photovoltaic material as low cost, high efficiency solar cells. In this work, two types of CdS/CdTe solar cells are investigated. One is fabricated by screen printing and sintering CdS and CdTe formation process. The other type is fabricated using CdS films deposited by chemical vapor deposition (CVD) and p-CdTe film deposited by close-spaced sublimation (CSS) method. By the analysis of the X-ray diffraction patterns, the orientation of the sintered CdS film and the sintered CdTe film is almost random, whereas the crystal structure of the CVD-CdS film is hexagonal, and strongly oriented. The CSS-CdTe film strongly oriented, too. Solar cells of 1 cm/sup 2/ with an efficiency of 15.05% under AM 1.5, have been prepared from CVD-CdS/CSS-CdTe films.

Sub-band image coding is considered to be a promising technique for high fidelity compression of high resolution images. In the traditional sub-band image coding algorithm where a scalar quantizer is used, high frequency sub-band signals are usually discarded, which incurs rather noticeable degradation of reconstruction quality. To solve this problem, the authors introduce improved permutation codes, developed by extending the concept of prototypal permutation codes into sub-band image-coding. Improved permutation codes are used to quantized high frequency sub-band signals. The simulation results demonstrate that improved permutation codes are more useful than an entropy-constrained scalar quantizer as a means for quantizing high frequency sub-band signals. An adaptive quantization technique combining improved permutation codes and entropy-constrained scalar quantizers is developed, and its usefulness is demonstrated by computer simulations. >

A new instability phenomenon in scaled CMOS devices is presented. Threshold voltage shifts caused by this phenomenon are observed in negative gate bias conditions. The shifts are depend on test temperatures, bias conditions applied to the device and channel lengths of devices. It is found that the activation energy of acceleration factor in this shift is between 1.0eV and 1.2eV. As a result of an analysis, this phenomenon may be found to be caused by moisture initially involved in a phosphosilicate glass passivation layer.

Life tests on aluminum interconnect showed that pattern with a large width and spacing can corrode faster than those with a smaller width and spacing. This paradoxical phenomenon was found on temperature, humidity and bias test at 85 to 140°C, 85%RH, and 0 to 150V, and can be explained by crack formation in the passivation layer induced by aluminum corrosion.

A MNOS non-volatile memory has many special features and a good marketability. In spite of that it is not widely used due to its undeveloped reliability. Life test experiments were done under various application conditions to obtain an exact reliability estimation for a MNOS memory. Result of these test imply the application of erase/ write cycles prior to retention life test experiments, which is preferable for a proper estimation of life time at field operation conditions. A screening procedure at high temperature for a short time becomes possible by applying a proper acceleration factor.

To improve the moisture resistance after soldering heat stress for SMD(Surface Mount Device), a new approach introducing the "Ion-exchange process" was succesfully tried out. In this approach, ion-exchanging material(usually called "ion-trap") is added to the molding compound substituting the highly active impurity+ ions+ in the compound by weak ones(ex. Cl- ? OH-, Na+ ? H+). By applying this process, the lifetime for both cathodic and Al pad corrosion becomes 1.5~3 times longer for the epoxy compounds tested.

A new failure wire crater was studied in surface mount devices. It is defined as a peeling-off phenomenon of the wire ball from the Si substrate or insulator when soldering heat stress is present. It only occurs when the package absorbs a significant amount of water before soldering. To analyze this phenomenon, conditions of water absorption, soldering heat stress, wafer process (metallization and insulator materials) and assembly process (wire bonding) were investigated. From these results, it is found that cratering occurs when the Si nodules of Al-Si metallization damage the insulator at wire bonding. >