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Current multi-core processors implement sophisticated hardware prefetchers, that can be configured by application (PID), to improve the system performance. When running multiple applications, each application can present different prefetch requirements, hence different configurations can be used. Setting the optimal prefetch configuration for each application is a complex task since it does not only depend on the application characteristics but also on the interference at the shared memory resources (e.g., memory bandwidth). In his paper, we propose DeepP, a deep learning approach for the IBM POWER8 that identifies at run-time the best prefetch configuration for each application in a workload. To this end, the neural network predicts the performance of each application under the studied prefetch configurations by using a set of performance events. The prediction accuracy of the network is improved thanks to a dynamic training methodology that allows learning the impact of dynamic changes of the prefetch configuration on performance. At run-time, the devised network infers the best prefetch configuration for each application and adjusts it dynamically. Experimental results show that the proposed approach improves performance, on average, by 5.8%, 6.7%, and 15.8% compared to the default prefetch configuration across different 6-, 8-, and 10-application workloads, respectively. [ABSTRACT FROM AUTHOR]

Advanced hardware prefetch engines are being integrated in current high-performance processors. Prefetching can boost the performance of most applications, however, the induced bandwidth consumption can lead the system to a high contention for main memory bandwidth, which is a scarce resource in current multicores. In such a case, the system performance can be severely damaged. This article characterizes the applications’ behavior in an IBM POWER8 machine, which presents many prefetch settings, varying the bandwidth contention. The study reveals that the best prefetch setting for each application depends on the main memory bandwidth availability, that is, it depends on the co-running applications. Based on this study, we propose Bandwidth-Aware Prefetch Configuration (BAPC) a scalable adaptive prefetching algorithm that improves the performance of multi-program workloads. BAPC increases the performance of the applications in a 12, 15, and 16 percent of 6-, 8-, and 10-application workloads over the IBM POWER8 default configuration. In addition, BAPC reduces bandwidth consumption in 39, 42, and 45 percent, respectively. [ABSTRACT FROM AUTHOR]

This paper aims at contributing to the specialized literature on the experimental characterization of metasurfaces (MTSs) reflectivity. The growing demand for angularly stable MTSs reinforces the relevance of the results under oblique incidence. Generally, reflection coefficient phase measurements are more challenging than the amplitude ones. Thus, an artificial magnetic conductor (AMC) is used to analyze the critical aspects for enlarging the angular margin that can be properly measured. The importance of the retrieving methodology along with the proposed data postprocessing is highlighted among the involved issues, according to the obtained results. The suitability of monostatic versus bistatic measurement setups for comparison with plane-wave simulation is studied. The aforementioned AMC is experimentally characterized using both setups providing relevant conclusions. The tradeoff between the manufactured prototype dimensions (to resemble the simulated infinite one) versus the required anechoic chamber size (to fulfill far-field (FF) conditions, i.e., the plane-wave incidence for the considered frequencies) is tackled. Indeed, a thorough literature revision shows that most authors do not have this key aspect into account. The relevance of the resulting error from comparisons between the near-field (NF) retrieved measurements versus plane-wave simulation results is unveiled. This is even more critical when the angular stability is analyzed, since the scattering patterns of the AMC are not conformed at NF distances, which makes the errors even greater. Consequently, noteworthy conclusions concerning the characterization of AMCs in particular and MTSs in general regarding FF or NF measurements and angular stability analysis will be presented. [ABSTRACT FROM AUTHOR]

Shared caches have become the common design choice in the vast majority of modern multi-core and many-core processors, since cache sharing improves throughput for a given silicon area. Sharing the cache, however, has a downside: the requests from multiple applications compete among them for cache resources, so the execution time of each application increases over isolated execution. The degree in which the performance of each application is affected by the interference becomes unpredictable yielding the system to unfairness situations. This paper proposes Fair-Progress Cache Partitioning (FPCP), a low-overhead hardware-based cache partitioning approach that addresses system fairness. FPCP reduces the interference by allocating to each application a cache partition and adjusting the partition sizes at runtime. To adjust partitions, our approach estimates during multicore execution the time each application would have taken in isolation, which is challenging. The proposed approach has two main differences over existing approaches. First, FPCP distributes cache ways incrementally, which makes the proposal less prone to estimation errors. Second, the proposed algorithm is much less costly than the state-of-the-art ASM-Cache approach. Experimental results show that, compared to ASM-Cache, FPCP reduces unfairness by 48 percent in four-application workloads and by 28 percent in eight-application workloads, without harming the performance. [ABSTRACT FROM PUBLISHER]

Recent proposals are based on classifying memory accesses into private or shared in order to process private accesses more efficiently and reduce coherence overhead. The classification mechanisms previously proposed are either not able to adapt to the dynamic sharing behavior of the applications or require frequent broadcast messages. Additionally, most of these classification approaches assume single-level translation lookaside buffers (TLBs). However, deeper and more efficient TLB hierarchies, such as the ones implemented in current commodity processors, have not been appropriately explored. This paper analyzes accurate classification mechanisms in multilevel TLB hierarchies. In particular, we propose an efficient data classification strategy for systems with distributed shared last-level TLBs. Our approach classifies data accounting for temporal private accesses and constrains TLB-related traffic by issuing unicast messages on first-level TLB misses. When our classification is employed to deactivate coherence for private data in directory-based protocols, it improves the directory efficiency and, consequently, reduces coherence traffic to merely 53.0 percent, on average. Additionally, it avoids some of the overheads of previous classification approaches for purely private TLBs, improving average execution time by nearly 9 percent for large-scale systems. [ABSTRACT FROM AUTHOR]

Virtual education raises to students and teachers important challenges, normally different to those faced in conventional education. In the context of virtual education, a question that remains to be solved is associated with the level of motivation possessed by the students during the course. Usually, at the School of Engineering in the University of Medellín, this issue is tackled through activities such as chats and forums. Mostly, these activities are not enough to motivate the student in the activities related with the learning process. This work proposes two motivation strategies based on gamification and constructivism. These strategies are validated in a course called programming fundamentals, taught to all bachelor degrees given in the School of Engineering. Results obtained through the experiments suggest that proposed strategies improve the student's performance and satisfaction in the course. Therefore, when teaching at the virtual scenario, using Information and Communication Technologies in the educational environment is not only the way to contact the student, it is the mean to develop pedagogical-didactic approaches that finally enrich the educational process and consequently motivate the student to perform well. [ABSTRACT FROM PUBLISHER]

Measurements are usually the final process of a device characterization and show whether the device works properly or needs some readjustments. Measurements are not a trivial issue; they require a lot of time and careful planning to perform them. There are many papers that deal with simulations and characterizations of the metamaterial absorber unit cell [1]-[6], but not all of them carried out the manufacture and measurement of the proposed prototypes. [ABSTRACT FROM AUTHOR]

On the one hand, performance and fault-tolerance of interconnection networks are key design issues for high performance computing (HPC) systems. On the other hand, cost should be also considered. Indirect topologies are often chosen in the design of HPC systems. Among them, the most commonly used topology is the fat-tree. In this work, we focus on getting the maximum benefits from the network resources by designing a simple indirect topology with very good performance and fault-tolerance properties, while keeping the hardware cost as low as possible. To do that, we propose some extensions to the fat-tree topology to take full advantage of the hardware resources consumed by the topology. In particular, we propose three new topologies with different properties in terms of cost, performance and fault-tolerance. All of them are able to achieve a similar or better performance results than the fat-tree, providing also a good level of fault-tolerance and, contrary to most of the available topologies, these proposals are able to tolerate also faults in the links that connect to end nodes. [ABSTRACT FROM PUBLISHER]

Most of the data referenced by sequential and parallel applications running in current chip multiprocessors are referenced by a single thread, i.e., private. Recent proposals leverage this observation to improve many aspects of chip multiprocessors, such as reducing coherence overhead or the access latency to distributed caches. The effectiveness of those proposals depends to a large extent on the amount of detected private data. However, the mechanisms proposed so far do not consider neither thread migration nor the private use of data within different application phases. As a result, a considerable amount of private data is not detected. In order to increase the detection of private data, we propose a TLB-based mechanism that is able to account for both thread migration and application phases. Simulation results show that the average number of pages detected as private significantly increases from 43 percent in previous proposals up to 79 percent in ours while keeping a reasonable TLB miss rate. Furthermore, when our proposal is used to deactivate the coherence for private data in a directory protocol, it improves execution time by 13.5 percent, on average, with respect to previous techniques. [ABSTRACT FROM PUBLISHER]