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It is undeniable that aerial/satellite images can provide useful information for a large variety of tasks. But, since these images are always taken from above, some applications can benefit from complementary information provided by other perspective views of the scene, such as ground-level images. Despite a large number of public repositories for both georeferenced photographs and aerial images, there is a lack of benchmark datasets that allow the development of approaches that exploit the benefits and complementarity of aerial/ground imagery. In this article, we present two new publicly available datasets named AiRound and CV-BrCT. The first one contains triplets of images from the same geographic coordinate with different perspectives of view extracted from various places around the world. Each triplet is composed of an aerial RGB image, a ground-level perspective image, and a Sentinel-2 sample. The second dataset contains pairs of aerial and street-level images extracted from southeast Brazil. We design an extensive set of experiments concerning multiview scene classification, using early and late fusion. Such experiments were conducted to show that image classification can be enhanced using multiview data.

In this work, a biosensor based on Localized Surface Plasmon Resonance (LSPR) system to detect the four serotypes of the Dengue Virus (DENVx), is presented and demonstrated. The numerical simulations of gold nanorods (GNRs) through Finite Element Method (FEM) supported by COMSOL Multiphysics, and the achieved experimental results, allowed us to understand the behavior of nanorods in interaction with biological elements during the detection process.

We propose a methodology to transparently estimate near-optimal application mappings aiming at increasing the Mean Workload to Failure (MWTF) in heterogeneous multicore processors. For that, we leverage an Artificial Neural Network (ANN) capable of estimating the vulnerability factor of RISC-V cores at runtime, which allows for efficient and dynamic application-to-core mappings targeting better MWTF and MWTF/energy tradeoffs. Results show that our ANN-based mapping yields very close-to-optimal solutions, with a difference in MWTF of only 3% when compared to the optimal mapping. When compared to a homogeneous architecture composed of only big cores, heterogeneous architectures may provide improvement in MWTF of up to 20.5% while impacting 12.2% on performance.

Current and emerging systems for high-throughput applications, such as machine learning, cloud computing, and real-time video encoding demand real-time processing computations, heavily constrained by latency and power requirements. To deal with the increasing computational complexity, designers may resort to approximate accelerators for error-resilient compute-intensive kernels to meet such requirements with acceptable deviation from the exact implementation. However, since time-to-market is crucial when dealing with evolving applications, technologies, and standards, hand-crafting approximate accelerators may impose prohibitive development time and cost overheads. In this scenario, approximate High-Level Synthesis (HLS) methodologies have been proposed to deal with the complexity of exploring approximation techniques. Nevertheless, current tools are not suitable for exploring throughput optimizations, being instead constrained to perform specific improvements on area, power, and performance. In this work, we propose the use of HLS to generate Pareto-optimal accelerators for throughput-constrained applications. Particularly, we present a throughput-oriented approximate HLS methodology that explores both delay and area optimizations to increase the reuse over time and parallelism of such accelerators. Results show that our method is able to improve throughput by up to 80 % with no additional area costs or to sustain the same throughput of the exact design with about 45 % less area while introducing manageable error for most applications. Moreover, our method can attain throughput improvements of up to 18% when compared with recent works focusing only on performance or area optimizations, with no additional costs.

Intermittent systems are ultra-low-power batteryless devices that are increasing in popularity. These systems operate with energy extracted entirely from the environment. Since most environments cannot ensure sufficient and steady power supply conditions, intermittent devices suffer from frequent power outages, where computation is interrupted due to the lack of energy. While numerous works have enabled intermittent computation via many different techniques, there are no versatile and configurable tools that ensure functionality, and rapid development/design space exploration. Therefore, in this paper, we present Firefly, an intermittent open-source framework for developing ultra-low-power devices based on the RISC-V ISA and the Rocket Chip. Firefly enables developers to modify and extend the project to satisfy their preference, i.e., memory technologies, intermittent environment configuration, and hardware modifications. By exploiting the versatility offered by the Firefly framework, we evaluate different memory technologies in an intermittent environment, showing that in many times PCRAM and RRAM will be the best choices to compose the design.

We propose a transparent and runtime methodology to increase the system’s Mean Workload to Failure (MWTF) in heterogeneous multicore processors. For that, we leverage an Artificial Neural Network that makes online predictions of the core’s Architectural Vulnerability Factor (AVF), which allows for reliability-aware application-to-core mappings. We experiment with different configurations of RISC-V cores and compare the MWTF of prediction-based mappings against the optimal oracle, showing that our proposed model provides MWTF as close as 5.6% to the oracle. We also compare homogeneous and heterogeneous multicores, showing that heterogeneity provides room for increasing the MWTF in up to 19.4%.

As newer video encoding standards are proposed, higher compression rates are attained at the cost of increasing computational complexity. Thus, achieving real-time video encoding for higher resolutions and frame rates becomes challenging, especially when considering costs in area and energy. Approximate accelerators can be used to alleviate the costs of critical kernels, such as motion estimation, but their design becomes costly when maintaining a short time-to-market is desirable, especially in a scenario of standards that evolve frequently. In this work, we propose the use of High-Level Synthesis (HLS) to quickly generate Pareto-optimal motion estimation approximate accelerators. We propose a throughput-aware approximate HLS tool able to attain area savings between 6% and 55% or improve the frame rate by between 5.5% and 78%, with PSNR reductions varying from 0.32 dB to 3.4 dB, respectively.

Due to the extremely rapid growth of the computing and IT technology market, commercial hardware made for the civilian, consumer sector is increasingly (and inevitably) deployed in security-sensitive environments. With the growing threat of hardware Trojans and backdoors, an adversary could perpetrate a full system compromise, or privilege escalation attack, even if the software is presumed to be perfectly secure. We propose a method of field stripping a computer system by empirically proving an equivalence between the trustability of the fielded system on one hand, and its comprehensive set of sources (including those of all toolchains used in its construction) on the other. In the long run, we hope to facilitate comprehensive verification and validation of fielded computer systems from fully self-contained hard-ware+software sources, as a way of mitigating against the lack of control over (and visibility into) the hardware supply chain.

This work demonstrates the first sputtered thin-film nickel-titanium (NiTi) shape-memory alloy (SMA) actuators combined with direct 3D printing of polymeric structures. Resulting actuators are fast to prototype, reliable and stable (up to 5000 cycles), and can utilize complex geometries challenging to achieve with conventional MEMS microfabrication. The actuator design uses 3D printed polymer as the passive layer in unimorph actuators, adding significant versatility to the actuator design. An actuator designed for high force-displacement was fabricated with a $15\ \ \mu \mathrm{m}$ thick polymer layer and characterized by applying currents up to 18 ma (7.3 mW, producing ∼156°C) resulting in a maximum displacement of $3.3\ \mu \mathrm{m}$ and ∼0.9 mN blocking force. Dynamic operation with falling/rising times of 20.1 ms/9.8 ms and 33.5 Hz maximum operation frequency was also demonstrated.

High-performance superscalar processors have been developed to satisfy the growing demand for processing modern applications. However, as the transistor size shrinks, the increase in vulnerability to soft errors poses a great challenge, since these effects have been proven to also affect ground-level safety-critical applications. Considering that vulnerability strategies may span across different layers of the system stack, we propose a mixed SW/HW-based design-time methodology aiming to achieve the best tradeoff between vulnerability and area/energy for superscalar processors. By injecting over 10 million faults in 12 significant micro-architectural structures to different versions of the complex BOOM OoO superscalar processor modeled with RTL accuracy, we show that SW-based protection techniques always reach an upper bound that may not be satisfactory. Then, we propose to insert extra low-level HW-based DMR protection at strategic micro-architectural points by reducing this task to the Knapsack Problem. In one of the evaluated cases, we optimally find the best structures to be protected with 55% area overhead to achieve a 95% vulnerability improvement for a quad-issue processor.

Efficient video coding techniques applied by modern video encoders - e.g. the High Efficiency Video Coding (HEVC) - enable the handling and sharing of digital videos content. The applied complex data-intensive algorithms, as the Motion Estimation (ME), pose severe constraints in terms of memory communication and energy consumption, especially for battery-powered devices. Thus, an evaluation using efficient memory hierarchies, exploring multiple cache configurations and the use of non-volatile memories (NVMs) as main memory, was performed. Our evaluation considered TZS algorithm, encoding FHD videos, under 32 different cache configurations, combined with three main memory technologies: DRAM, STTRAM, and ReRAM. The best cache configurations were selected in terms of lowest total energy consumption, moreover, different energy savings were achieved using non-volatile memories as main memory, varying from 33.4% to 57.6%, for STTRAM and ReRAM, respectively, with ReRAM presenting the best energy results and reducing the optimal cache size.

High-performance superscalar processors have been adopted to satisfy the rising demand for processing applications of ever-growing complexity. This extra complexity, added to the increasing vulnerability of transistors due to technology scaling, poses a great challenge since these effects have also been proven to affect ground-level safety-critical applications. To increase microarchitectural resilience, designers may adopt Dual Modular Redundancy (DMR), which offers full fault detection. However, given that DMR incurs in high area and energy overheads, we propose a design-time methodology aiming to achieve the best tradeoff between resilience and area overhead, decreasing DMR costs and maintaining acceptable detection levels for such a complex design. This is done by adopting the Knapsack Problem (KSP) as a heuristic to identify the optimal micro-architectural structures that should be duplicated to achieve target resilience with the smallest possible area overhead. By injecting over 800k faults in 12 significant micro-architectural structures of different versions of the complex Berkeley Out-of-Order Machine (BOOM) superscalar processor modeled with RTL accuracy, we compare this optimal strategy against a greedy one, showing that 90% of vulnerability reduction may be achieved with 50.6% and 107.8% area overheads for the optimal and greedy strategies, respectively.

The identification of bridges in major infrastructure works is crucial to provide information about the status of these constructions and support possible decision-making processes. Typically, this identification is performed by human agents that must detect the bridges into large-scale datasets, analyzing image by image, a time-consuming task. In this paper, we propose a novel tool to perform bridge detection and identification in large-scale remote sensing datasets. This tool implements a deep learning-based algorithm, the Faster R-CNN (Regions with CNN features), a technique that is the current state-of-the-art for many object detection and identification applications. Since deep training usually requires a lot of data, we also created a bridge image dataset, composed of remote sensing images from around the globe. The proposed tool was encapsulated into an ArcGIS plugin in order to facilitate its use by non-programmer users.

Low-Density Parity-Check (LDPC) codes have been used in many communication standards due to their capacity-approaching performance with feasible decoding architectures. Field-Programmable Gate Arrays (FPGAs) have been shown to be appropriate for the implementation of LDPC decoders, due to their ability to exploit the fine-grained parallelism found in such codes, as well as due to their reconfigurability, which allows to easily adapt the decoder to different codes. The susceptibility of FPGAs to faults affecting their configuration memories, however, demands specific fault tolerance strategies when these devices are used in harsh environments, such as aerospace applications, or even in ground-level critical systems. Thus, in this work we present a characterization of the behavior of LDPC decoders when subject to configuration errors and show that a single error can substantially degrade decoding performance, differently from what is observed in application-specific circuits. Based on this characterization, we propose a cost-effective fault tolerance scheme able to cope with faults in the FPGA fabric. Identifying the most critical components allowed reducing performance degradation by 89 % while only covering 55 % of their area.

A dielectric rod antenna is designed in Kuband using established principles for designing maximum gain surface wave antennas in free space as in [1]. The design principles are modified to their most general form and applied to the design of three dielectric rod antennas embedded in a dielectric cladding of different dielectric constant: ∊ r = 1.0 (free space ”cladding”), ∊ r = 1.6 (3D printed ABS with 50% in-fill), and ∊ r = 2.6 (3D printed ABS with 100% in-fill). The antennas are simulated and measured to determine agreement between them and thereby validate the design procedure.

A new hands-free approach to antenna fabrication is presented here, with laser folding used to fabricate a prototype 94.5 GHz end-fed longitudinal shunt slot array (EFLSSA) antenna. Laser cutting and folding was demonstrated for creation of 3D metal antennas as a low cost, rapidly iterated alternative to machining techniques such as electro-discharge machining (EDM) and die forming. The technique used is based on a low cost and power 1064nm marking laser. All cutting and folding is done completely remotely using the laser itself from a blank sheet of metal foil. The demonstrated waveguide slots are cut to sub-micron precision, and modelling of the resulting structure is also presented.

The low conductivity of 3D printed conductive lines is one of the main obstacles in successful 3D printed electronics. These low conductivities lead to lossy transmission lines, poorly performing antennas, and pose many challenges from a circuit design prospective. In this work, two techniques are demonstrated for improving the conductivity of 3D printed silver paste: photonic sintering and selective electroplating. The silver lines were direct write extruded onto a FFF 3D printed substrate and dried before curing. As an alternative to traditional heat curing, parts printed on a uniaxial double sloped 3D surface are photonically sintered using a commercial PulseForge system, resulting in an increase of the line conductivity by 806%. The lines were then electroplated in a copper plating solution, selectively depositing a layer of copper to obtain a further increase in the line conductivity of 886%, a total improvement of 7,150%. Line conductivities were verified using a 4-point measurement setup along with an X-Ray CT scanning system to determine the cross sectional area of the lines. Bringing high resolution 3D printed metal lines closer to bulk conductivities is critical in enabling 3D printed RF and high performance electronics.

Densely connected networks for classification enable feature exploration and result in state-of-the-art performance on multiple classification tasks. The alternative to dense networks is the residual network which enables feature re-usage. In this work, we combine these orthogonal concepts for encoder-decoder architectures, which we call Dual-Path Dense-Block Network (DPDB-Net). We introduce a dense block which incorporates feature re-usage and new feature exploration in the encoder. Moreover, we discuss that feature re-usage by the residual network architecture leads to a feature map explosion in the decoder and, thus, is not advantageous in this part of the network. We evaluated our proposed architecture in multiple segmentation tasks and report state-of-the-art performance on the Freiburg Forest dataset and competitive results on the Cam Vid dataset.

Since superscalar processors lead the market, their resiliency evaluation by means of fault injection grows in importance. Fault injection strategies usually trade-off their levels of accuracy: low-level HW-based methods are accurate, but very expensive, need special equipment and the actual hardware, and lack controllability; while high-level simulation-based strategies are flexible, fast, easily accessible and have high controllability, but are not accurate since they are based on models that do not always reflect the low-level implementation, mainly when it comes to complex designs like out-of-order multiple-issue processors. In this work, we propose a cycle-accurate fault injection platform for superscalar processors, which has a smart checkpointing mechanism to accelerate injection time, attenuating the short-comings imposed by the aforementioned fault injection methods while providing the same level of abstraction as detailed RTL models. Leveraging from this new platform, we evaluate a complex and parameterizable Out-of-Order processor (BOOM) by experimenting with different issue widths and analyzing the sensitivity of several hardware structures of the processor.