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This paper presents a widely tunable bandpass filter (BPF) that can autonomously adapt its gain to the power level of signals present within its passband. Similar to outphasing amplifiers, the filter realizes reconfigurable gain by splitting the input signal using two N-path filters into two components of equal and opposite phases (±Φ). The components are then subtracted at the filter output to reconstruct the original signal with a gain value proportional to sin(Φ). For input signals below -10 dBm, the BPF behaves as a conventional 4th-order filter that is tunable from 0.4 GHz to 1.5 GHz. Above the -10-dBm limit, the filter gain decreases by approximately -10 dB for each +10-dB increase in the input power to maintain the filter output power at a limiting level of -9.4 dBm. Unlike classical adaptive filters, the tunable filter achieves a sublimiting in-band IIP 3 of +8.36 dBm and an out-of-band IIP 3 of +27 dBm. The filter is implemented in 0.18-µm CMOS and has a NF of 11 dB.

This paper reports the first widely tunable N-path frequency-selective limiter (FSL). Eight stagger-tuned 4-path filters are alternately summed to establish a 4-channel BPF with a steep roll-off between the passband and the stopband. The limiting action of an FSL is realized by autonomously modulating the frequency separation between each of the two 4-path filters within a channel to control the channel's passband gain. For input signals below −2 dBm, the FSL behaves as a conventional BPF with a 250 MHz bandwidth. At each input spectral component exceeding this limiting threshold, the FSL provides a variable notch in its passband with increasing attenuation of −10 dB for each +10-dB increase in the input component power to maintain the troubling tone output power below −1.3 dBm. The implemented 4-channel FSL using $0.18-\mu \mathrm{m}$ CMOS is tunable from 0.3 GHz to 1 GHz and achieves a NF of 14.5 dB.

Frequency Modulated Continuous Wave (FMCW) radar has extensive areas of application for both civil and military use due to its good performance and detection capabilities. FMCW radar signal processing is based on two main modules; Moving Target Indicator (MTI) and Two-Dimensional Fast Fourier Transform (2D-FFT). Detection performance of FMCW radar is degraded due to the attenuation of the signals come from slowly moving targets with small visible Doppler frequencies. Also, the detection degradation of the targets whose beat frequency do not lie on the FFT grids. These problems have been introduced and overcome. In this paper, a complete design and implementation of LFMCW radar signal processor incorporating the solution of these problems are introduced on a field programmable gate array (FPGA) to facilitate real time processing. Simulation and experimental measurement are found to be identical illustrating the capability of the applied methods. The hardware implementation includes generation of the digital sawtooth waveform, Dechirping process,2D_FFT processing, Windowing, MTI, Single Delay Line Integrator and off pin filter.

This paper presents an N-path switched-capacitor rectifier which is capable of realizing staircase conjugate impedance matching, without the use of inductors, to maximize the power transfer from a piezoelectric transducer. Measurements of the 0.18μm CMOS prototype demonstrate 13.9× improvement in extracted power compared to an ideal full-bridge rectifier.

This paper presents the application of Compressive Sensing (CS) theory in radar signal processing. CS uses the sparsity property to reduce the number of measurements needed for digital acquisition, which causes reduction in the size, weight, power consumption, and the cost of the CS radar receiver. A well-known CAMP algorithm was used to reconstruct the compressed sparse LFMCW radar signal and improves its Signal-to-Noise Ratio. An Adaptive recovery CAMP algorithm, which had been proposed to deal with pulsed radar signal instead of the CAMP algorithm, in order to manage the problems of the limited number reconstructed targets, according to the incoherence property of the traditional CAMP algorithm, as well as reduce the complexity of the reconstruction algorithm. In present work, the Adaptive recovery CAMP algorithm will be applied to the LFMCW radar signal to enhance the detection performance and the number of detected targets in the LFMCW radar. Simulation results are done to evaluate the proposed algorithm compared with the traditional algorithm, for detection performance evaluation between the proposed algorithm and the traditional algorithm using the Receiver Characteristic Curve (ROC), the number of detected targets, the resolution performance, and the complexity evaluation.

Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (V out ) at the desired level (V ref ), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size ( g LSB) as the code is increased, the output voltage step, v LSB, does not; in fact, v LsB is nonlinear: ∼G L V out × G LSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, e ss = V eef − V out ≈ ± g LSB/G l χ V u!op , as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, V drop = V in − V oitt , and at small loads, G l . As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ I L dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2N-6, 7 at V eef =VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (T R ), quiescent power (IQ), and area.

This paper combines application of Compressive Sensing theory in radar signal, and the approach of the Xampling. Based on the characteristic of sparse radar signal, it can be sampled at Finite Rate of Innovation (FRI) [1], Xampling converts high dimensional signal to a lower dimensional signal using Fourier coefficients directly from analog signal [2]. A well-known CAMP algorithm was used to reconstruct the under sampled sparse radar signal and improves its Signal-to-Noise Ratio in case of received radar signal has a high SNR [3]. In present work, a proposed algorithm called Adaptive CAMP algorithm is applied to the radar signal in order to deal with the problem of the false alarms that appear in reconstructed radar signal from the CAMP algorithm in case of received low SNR. The performance of the Adaptive CAMP algorithm as well as the CAMP algorithm is evaluated using the Receiver Characteristic Curve (ROC) to compare the proposed design with the CAMP algorithm in case of low SNR.

Cognitive Radio (CR) can solve the spectrum scarcity problem; also Compressive Sensing (CS) minimizes the required sampling rate lower than the ordinary Nyquist rate. In this work, a combined technique for detection and frequency estimation for Slow Frequency Hopping Spread Spectrum (SFHSS) based on CS and FFT Averaging Ratio (FAR) spectrum sensing algorithm is introduced. The proposed algorithm is merging FAR algorithm and Orthogonal Matching Pursuit (OMP) algorithm in order to enhance the signal detection capability. Using OMP is preferred in the proposed algorithm because it has the minimum complexity and sufficient performance among the most of CS reconstruction algorithms. Since it is composed of OMP and FAR, the proposed algorithm is called Enhanced Orthogonal Matching Pursuit (EOMP). EOMP operation is compared with both Incoherent Detection and Estimation Algorithm (IDEA) and Cosine Similarity (COSSIM) techniques for detection and frequency estimation for single primary user. EOMP has a good signal detection and frequency estimation performance compared with IDEA and COSSIM techniques but with increasing in sensing time, which can be compensated using parallel processing.

Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32–0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have shown rapid response times (e.g. T R = 0.65ns [2]) and excellent steady-state performance, they fail to operate at the low input voltages, V IN , typically supplied to such SoCs via either a high-efficiency switching DC-DC converter or an external harvesting source (e.g., V IN = 0.5V). On the other hand, digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. However, conventional DLDOs respond slowly to large current steps, especially at low voltages (e.g., T R = ∼44ns, 57.1ns, and 4µs at V IN =1V [3–5], and 20µs at V IN =0.5V [1]). Furthermore, they suffer from limited dynamic range over which the load is regulated and stable (e.g. s , this comes at increased power consumption and, importantly, reduced loop stability. To address these issues, this paper presents a 0.5V 0.0023mm2 recursive all-digital LDO (RLDO) in 65nm with hybrid PD-SAR and PWM duty control that achieves 15.1ns and 100ns response and settling times, respectively, while maintaining 5.6mV/mA load regulation and loop stability across a 20,000× dynamic load range, eclipsing state-of-the-art active area, response time, settling time, and dynamic range metrics across prior-art digital LDOs by over an order of magnitude.

Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactance of global clock networks at a given resonance frequency, f o , have been proposed. Conventionally, such schemes are only suitable at high multi-GHz frequencies in order to be able to place the employed inductors on chip [1, 2]. Since many modern energy-efficient SoC designs optimize for clock frequencies DD to the MHz and near-threshold regimes, respectively, there is a need to develop low-power clock distribution schemes that can work across increasingly wider operating ranges. Recent work in quasi-continuous resonant clocking has proposed intermittent cancelation of global clock-tree capacitance during edge transitions, however, such techniques require large off-chip inductors and are limited to 0.98MHz [3] and 150MHz [4], respectively, owing to the need to operate well below resonance (i.e., o /10). Thus, while prior-art has shown power reduction for targeted applications, they all require large on- or off-chip magnetics, and do not meet the MHz-to-GHz frequency-range needs of modern DVFS-enabled SoCs. To address these problems, this paper introduces a fully integrated adiabatic clocking scheme that efficiently synthesizes n-step clock waveforms from 1MHz to 2GHz via a switched-capacitor DC-AC multi-level inverter topology, theoretically reducing power by 1/n without using any magnetic component.

This paper presents a DC-RF power inverter that efficiently synthesizes high-voltage RF waveforms directly from a battery voltage using thin-oxide CMOS switches. Instead of stacking transistors or employing large inductive transformation ratios, high output power is generated by switching individual class-D power amplifier (PA) cells in a 2-phase house-of-cards (HoC) topology to provide voltage addition of the cells outputs without exceeding device voltage ratings, effectively resulting in a solid-state RF impedance transformer. High-efficiency at backoff is then achieved by capacitively combining the output of two HoC networks nominally set to generate different amplitudes, enabling voltage-mode Doherty-like backoff without a bulky transmission line. The PA is implemented in 65nm bulk LP CMOS, operates from 4.8V, and provides a battery-to-RF efficiency above 40% at both 23dBm and 6dB backoff at 720MHz.

Application of Compressive Sensing (CS) in Linear Frequency Modulation Continuous Wave (LFMCW) radar had been investigated and proved by the authors in [8]. An approach, namely architecture 1, had been evaluated by the authors in [11] which dependent mainly on applying CS in range direction. But there is a limitation on the number of the detected targets in range. So, in the present paper, a new approach for applying CS in LFMCW radar signal processing, namely architecture 2, is introduced depends on apply CS in azimuth direction (range sweeps). The reduction in range sweeps is performed using a Pseudo Random (PN) sequence in Azimuth according to the required reduction ratio in range sweeps. The information of the received radar signal (target range and speed) are reconstructed by the use of Complex Approximate Message Passing (CAMP) reconstruction algorithm. Performance of the proposed LFMCW radar signal processors based on CS (architecture2) is evaluated and compared to that of both the traditional one based on Fast Fourier Transform (FFT)) and architecture 1 from points of view of detection performance through Receiver Operating Characteristics (ROC) curves, resolution performance and hardware complexity. The proposed approach (architecture 2) is designed and implemented using Field Programmable Gate Array (FPGA).

Modern SoC designs employed in battery-life-constrained mobile applications feature multiple power domains to dynamically scale power-performance trade-offs in response to application demands. Since each power domain requires a DC-DC converter, and since low-power mobile applications are also typically area-constrained, the employed DC-DC voltage regulators must: 1) be fully integrated, 2) support high efficiency across large dynamic current ranges spanning high-power active modes to low-power sleep modes where the overhead of complex control or multi-phasing is not feasible [1], and 3) support high power density to occupy minimal area overhead. Unfortunately, achieving both high efficiency and power density is difficult: integrated magnetic converters have limited efficiency and do not leverage CMOS scaling, while switched-capacitor (SC) converters suffer from fundamental power density-efficiency trade-offs due to ½C(ΔV)2f-based slow-switching-limit (SSL) losses. While recent work has employed high-density capacitors using ferroelectric or deep-trench technologies to achieve both high efficiency and high power density [2,3], such capacitor technologies are not available in all processes, and SSL losses still restrict the power density-efficiency trade-off, even with further scaling. Stacked-domain (SD) converters attempt to address this trade-off by achieving DC-DC conversion via stacked loads [4]; however, efficiency and density of SD converters approach the performance of the underlying charge-balance DC-DC converter required under load mismatch conditions, limiting the benefits of the SD approach for practical loads.

This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, realizing the widest resonant operating range reported in CMOS. A frequency-scaled gear train SC topology is introduced that enables soft-charging of all flying capacitors through one inductor at any arbitrary binary ratio by eliminating the inter-stage decoupling required in prior-art. Gear ratio modulation is proposed to control the resonance Q-factor, and hence the regulator can be gracefully transitioned from a resonant converter to a fully-capacitive SC, enabling > 24,000x output current range. For the same footprint, the converter achieves up to 14.4% and 12% efficiency improvements over co-fabricated SC and 3-level buck converters, respectively, while operating with a peak efficiency of 73.3% and current density of 0.14 A/mm2 in 0.18 μm bulk.

A switched-capacitor (SC) PMIC is presented that achieves up to a 6.6-bit resolution with only 5 flying capacitors for inductive PMIC replacement. The flying capacitors are reused in a frequency-scaled gear train as well as charge-feedback SC topologies to attain a 2.4× reduction in capacitors number compared to prior art. In 0.25μm bulk, the PMIC operates from an input voltage of 2.5–5V, can generate an output voltage ranging from 0.2–2V, and features an average efficiency of 90.2% across the entire range and a peak efficiency of 95.5%.

This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled SC converter efficiency, where it is found that the efficiency scales inversely with the product of the chip clock frequency and the MOSFET intrinsic delay. Through a derived numerical model of the SC power density, it is shown that a ∼ 0.5 W/mm2 SC density is sufficient to satisfy portable SoC power management needs with over 80% SC efficiency across the International Technology Roadmap for Semiconductors. This is at minimal area penalty by utilizing the nominally required 0.5 nF/mm2 decoupling capacitance for supply integrity.

The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can help achieve these goals in load circuits, though generally at the expense of increased DC-DC converter size (through use of external inductors) or loss (through linear regulation). While switched-capacitor (SC) DC-DC converters can offer conversion in small fully integrated form factors [1-5], their efficiencies are only high at discrete ratios between the input and output voltages. To increase an SC converter efficiency across its output voltage range, multiple conversion ratios can be utilized to realize a finer output voltage resolution. For instance, many converters employ a small handful of conversion ratios [1-4]. However, more conversion ratios are generally necessary to achieve high efficiency across the wide output range necessary for DVS, as converter efficiencies can otherwise fall by more than 20% between unloaded ratios [1-4]. Unfortunately, increasing the number of ratios beyond a small handful using standard topologies can significantly increase the number of components, escalating converter complexity and adding losses in the additional switching elements. To overcome this, a successive approximation (SAR) SC topology was proposed in [6] which cascades several 2:1 SC stages to provide a large number of conversion ratios with minimal hardware overhead. However, the linear cascading of stages introduces cascaded losses, limiting overall efficiency. For example, the minimum Rout is more than 30X Rout of a similar ratio Series-Parallel topology using the same silicon area. Additionally, current density is limited to that of a single stage, and capacitance utilization can be low for many conversion ratios.

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 2∶1 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to evaluate different loss components in order to find the optimal design point of highest conversion efficiency. This optimization method is verified through SPICE simulations on a 2∶1 SC power stage in 65-nm CMOS process.

A novel technique to remove the slow-switching-limit (SSL) loss in switched-capacitor (SC) dc-dc converters is presented. A small series inductor is cascaded with an SC converter causing adiabatic charging of the converter's energy-transfer capacitors. In this work, the theory and necessary conditions for SSL loss elimination through an inductive output filter are derived. The new topology enables high efficiency for on-die dc-dc converters while maintaining reasonable energy density. A 2:1 SC converter is built in 65-nm CMOS process to validate the analysis methods and asses the proposed technique. The proposed adiabatic charging enhances the SC efficiency by 3.3 % with only 13 % area overhead, which otherwise requires doubling the capacitor area.

A novel digital comparator topology is presented. Using transistors' ratio, a new fixed comparison level that can be programmed is introduced. An all-digital flash A/D converter is built using the proposed comparator topology. Building an N-bit flash A/D converter using the proposed M-bit digital A/D converters reduces the needed power and area by a factor of 2M; as compared to old topologies. It is shown that a 9-bit resolution flash A/D converter, built using 2-bit digital A/D converters, needs only the area and power of a 7-bit A/D converter that is constructed using old comparator topologies. Further reduction can be achieved if a 4-bit digital A/D converter is used to build the 9-bit flash A/D converter, where the required power and area are divided by 16.

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVR's switch current to the load current on a cycle by cycle basis. A 2-phase 3∶2 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA converter, the proposed mitigation loop reduces the peak-to-peak output ripple from 330 mV p-p to 17 mV p-p , using total output capacitance of 4 nF/A. In addition, the proposed technique yields excellent regulation transient response.

A novel double-bound hysteretic control of multi-phase switched-capacitor (SC) converters is presented. The technique adjusts the number of interleaved phases with the output load to significantly reduce the operating frequency of the control comparator, enabling the practical application of hysteretic control with large number of interleaved phases. Using the proposed technique, the maximum required speed of the hysteretic comparator is reduced from 7.3Ghz to 1.8Ghz in a 16-phase 2∶1 SC converter, designed in 65-nm CMOS process. In addition, the achieved dynamic response with such control is much faster than any reported integrated converter. For a 1.2-V input voltage and 0.45-V output voltage, the regulator enables a 35-mV p-p output droop for a 50% load step, without using a decoupling capacitor. In addition, the output for a 100-mV input reference step settles in 2.8-ns. The SC converter's efficiency is not affected by such reconfigurable interleaving scheme and reaches 81%.

A novel double-bound hysteretic regulation scheme to control multi-phase interleaved Switched-Capacitor DC-DC converters is presented. The control scheme adjusts the number of interleaved phases with the SC converter's switching frequency to significantly reduce the required operating frequency of the control comparator, enabling the practical application of hysteretic control with large number of interleaved phases. A 16-phase 2:1 SC converter is designed in 65-nm TSMC low-power CMOS process using the proposed technique. The converter with the new hysteretic control achieves fast dynamic response under fast varying load currents.

A novel low dropout (LDO) voltage regulator compensation technique is demonstrated. A parallel feedback path is used to insert a zero at approximately three times the output pole. The parallel feedback consists of passive elements only and occupies small area. The proposed technique completely eliminates the output pole at different load conditions and results in high LDO bandwidth, which achieves fast output tracking of the input reference and fast recovery of sudden load changes. Moreover, the output pole elimination at different load conditions enables the potential scaling of the error amplifier quiescent current with the load without compromising stability. The proposed LDO has been implemented in 65-nm TSMC low-power CMOS process, and achieves 0.24-ns response time at 94% current efficiency. For a 1.2-V input voltage and 1-V output voltage the regulator enables 79mVp-p output droop for a maximum load step.

A novel digital comparator topology is presented. The proposed digital comparator cell uses transistors' ratio to program a fixed comparison level. A double-bound hysteretic control comparator, for DC-DC converters, is built using the proposed digital comparator cell. The hysteretic-band width variation, due to process effects, decreases with increased preamplifier stage gain and constitutes a fixed ratio of the hysteretic-band width. The proposed comparator does not require offset cancellation circuits, which reduces power consumption as well as the die area and increases the comparison speed. In addition, one preamplifier and one reference generation circuit are needed to build the double-bound comparison levels. The proposed topology also does not require a sampling clock. A prototype hysteretic control comparator is implemented in 65-nm TSMC low-power CMOS process. The hysteretic-band width exhibits a maximum variation of 300 μV for a 10 mV width. The comparator dissipates 80 μA of ground current to sample a 1.5 GHz input signal.