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© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Wearable bioimpedance is a technique proposed to estimate breathing parameters such as respiratory rate (RR). However, its potential application lies in clinical investigation of daily-life activities like walking. This study evaluated the effect of the walking interference on the estimation of breathing parameters. 50 chronic obstructive pulmonary disease patients performed static and active measurements during thoracic bioimpedance acquisition. The static measurements included respiratory airflow for reference. The active measurements were used to estimate the walking interference from bioimpedance, and the obtained signals were added to static measurements for comparison with the reference. Afterward, we applied four different preprocessing methods to remove this walking interference and the resulting signals were used to detect the respiratory cycles and estimate breathing parameters (inspiratory time, expiratory time, duty cycle, and RR). The methods performed differently in terms of accuracy and mean average percentage error (MAPE), showing the need for specific preprocessing for active measurements. Furthermore, the MAPE values in the RR estimation were close to 3 % indicating that breathing parameters can be accurately estimated during walking. Accordingly, the present study reinforces the applicability of wearable bioimpedance for respiratory monitoring. Clinical relevance- This study exhibits the suitability of wearable bioimpedance to estimate accurate breathing param-eters during walking activities. This work was supported in part by the Universities and Research Secretariat from the Generalitat de Catalunya under Grant GRC 2017 SGR 01770 and, GrantFI-DGR, in part by the Agencia Estatal de Investigación from the Spanish Ministry of Science, Innovation and Universities and the European Regional Development Fund, under the Grant RTI 2018 098472B-I00, and in part by the CERCA Programme/Generalitat de Catalunya.

Three-dimensional integrated circuits promise power, performance, and footprint gains compared to their 2D counterparts, thanks to drastic reductions in the interconnects' length through their smaller form factor. We can leverage the potential of 3D integration by enhancing MemPool, an open-source many-core design with 256 cores and a shared pool of L1 scratchpad memory connected with a low-latency interconnect. MemPool's baseline 2D design is severely limited by routing congestion and wire propagation delay, making the design ideal for 3D integration. In architectural terms, we increase MemPool's scratchpad memory capacity beyond the sweet spot for 2D designs, improving performance in a common digital signal processing kernel. We propose a 3D MemPool design that leverages a smart partitioning of the memory resources across two layers to balance the size and utilization of the stacked dies. In this paper, we explore the architectural and the technology parameter spaces by analyzing the power, performance, area, and energy efficiency of MemPool instances in 2D and 3D with 1 MiB, 2 MiB, 4 MiB, and 8 MiB of scratchpad memory in a commercial 28 nm technology node. We observe a performance gain of 9.1% when running a matrix multiplication on the MemPool-3D design with 4 MiB of scratchpad memory compared to the MemPool 2D counterpart. In terms of energy efficiency, we can implement the MemPool-3D instance with 4 MiB of L1 memory on an energy budget 15% smaller than its 2D counterpart, and even 3.7% smaller than the MemPool-2D instance with one-fourth of the L1 scratchpad memory capacity., Accepted for publication in DATE 2022 -- Design, Automation and Test in Europe Conference

Spin-transfer torque magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for an energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using an STT-MRAM model, which is calibrated using 1Mbit characterized array. Results show that our proposed architecture for binary neural networks (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130× performance improvement for the text encryption compared to the software implementation on Intel Haswell processor.

The Fast Fourier Transform (FFT) is an efficient algorithm widely used in digital signal processing to transform between the time domain and the frequency domain. For fixed-point VLSI implementations, dynamic range growth inevitably occurs at each stage of the FFT operation. However, current methods either waste bitwidth or consume excessive resources when dealing with the dynamic range growth issue. To address this issue, we propose an efficient scaling method called Scaling Information Propagation (SIP) to alleviate the problem of dynamic range growth, which makes full use of bitwidth with much less extra area consumed than the state-of-the-art solutions. In two consecutive transform operations, the SIP method extracts scaling information and makes scaling decisions in the former transform, then executes those in the latter one. We implement the FFT's VLSI architecture in the orthogonal frequency division multiplexing (OFDM) and the holographic video compression (HVC) systems to verify the SIP method. Compared to the state-of-the-art, experimental results after VLSI synthesis show that our method achieves 9.38% energy reduction and 8.36% area savings when requiring 1.02 × 10-7 bit error ratio (BER) of the OFDM system, and 33.47% energy reduction and 30.98% area savings when requiring 20dB signal-to-noise ratio (SNR) of the HVC system, respectively.

© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works Many studies have focused on novel noninvasive techniques to monitor respiratory rate such as bioimpedance. We propose an algorithm to detect respiratory phases using wearable bioimpedance to compute time parameters like respiratory rate, inspiratory and expiratory times, and duty cycle. The proposed algorithm was compared with two other algorithms from literature designed to estimate the respiratory rate using physiological signals like bioimpedance. We acquired bioimpedance and airflow from 50 chronic obstructive pulmonary disease (COPD) patients during an inspiratory loading protocol. We compared performance of the algorithms by computing accuracy and mean average percentage error (MAPE) between the bioimpedance parameters and the reference parameters from airflow. We found similar performance for the three algorithms in terms of accuracy (>0.96) and respiratory time and rate errors (

Continuous and non-invasive cardiovascular monitoring has gained attention due to the miniaturization of wearable devices. Particularly, wrist-worn photoplethysmography (PPG) sensors present an alternative to electrocardiogram recording for heart rate (HR) monitoring as it is cheaper and non-intrusive for daily activities. Yet, the accuracy of PPG measurements is heavily affected by motion artifacts which are inherent to ambulatory environments. In this paper, we propose a low-complexity LSTM-only neural network for HR estimation from a single PPG channel during intense physical activity. This work explored the trade-off between model complexity and accuracy by exploring different model dataflows, number of layers, and number of training epochs to capture the intrinsic time-dependency between PPG samples. The best model achieves a mean absolute error of 4.47 ± 3.68 bpm when evaluated on 12 IEEE SPC subjects.Clinical relevance- This work aims to improve the quality of HR inference from PPG signals using neural network, enabling continuous vital signal monitoring with little interference in daily activities from embedded monitoring devices.

This work studies the performance of a Ge-based plasmonic detector with carrier mobility and lifetime variation. The performance is evaluated in terms of the detector's dark current, photocurrent, and detection bandwidth.

In this paper, we present a power, performance, area and cost (PPAC) analysis for large-scale 3D processor designs based on wafer-to-wafer bonding. From the evaluation of our cost model, we investigate a typically disregarded opportunity in 3D that is area savings due to buffer savings and better routability, offering unexpected cost savings. We explore the viability of this factor with the feedback of a state-of-the-art 3D memory-on-logic implementation flow. We show how this affects the PPAC of full-chip GDS implementations of a large-scale manycore processor design. Experiments show that our memory-on-logic 3D implementation offers 7% silicon area savings, resulting in 53.5% footprint reduction. We also obtain a 40% power-performance-cost improvement compared with 2D counterparts.

Integrating and operating PV in a system-efficient way is the key to increasing penetration levels to evolve toward a more sustainable and clean energy system. Reliable generation forecasting is the solution to tackle fluctuations in PV power generation and its negative effects on power systems and energy markets. Clouds play a key role in solar power, so cloud detection is important in PV power generation forecast. A color-based cloud detection algorithm is proposed in this paper. It considers 12 different color channels together with the K-means algorithm to detect clouds in sky images from an All-Sky Camera. The result of the proposed method has been compared to both classic and state-of-the-art methods. The experimental results show that the proposed approach has better performance in comparison to state-of-the-art methods.

Precise PV energy yield estimation is critically dependent on an accurate temperature estimation method. This paper experimentally investigates the accuracy of three commonly used thermal modelling methods. Detailed sensitivity analysis of yearly, monthly, daily and intraday time resolution reveals that the actual data are clearly dependent of day-type and weather parameters. However, the proposed methods struggle to estimate temperature with varying irradiance or wind speed. During the summer months, on intermittently cloudy days the intraday mismatch can be as high as 25°C, whereas on clear sky days it can be below 10°C. Applying these methods for short term estimation of any day type can lead to a large error in energy yield estimation. Further adaptation is required to propose estimation methods which can properly handle different day types and weather fluctuations.

In the past few years, the demand for computationally intensive applications, such as digital signal processing or convolutional neural networks, has grown exponentially. As they often rely on a significant number of multiply-and-accumulate cells, it is crucial to optimize their area and cost. Recently, a 3D Nanofabric flow has been proposed, where logic circuits are designed by stacking N identical vertical tiers on top of each other. Exploiting identical layers allows a fabrication process similar to the Vertical-NAND flash, where all the layers can be patterned at once. While the 3D Nanofabric flow presents several layout constraints (single metal routing and identical vertical layers), it can decrease the area by around one order of magnitude, leading to area-efficient and cost-effective circuits. In this paper, we propose to use the 3D Nanofabric process flow to design low-area multipliers. As multipliers can be designed using a regular array organization, we show how they can be spread across multiple vertical layers using the 3D Nanofabric flow, while respecting the different layout constraints. We then provide thorough circuit-level evaluations, including parasitics, to showcase the benefits of our proposed 3D multipliers at the circuit-level. We show that by stacking up to 64 layers to build a 64-input bit multiplier, the area and area-delay- product can be decreased by 28.6x and 25.5x, respectively, compared to a traditional 2D implementation using a 28nm FDSOI technology, with only a 10% and 35% delay and power consumption overheads, respectively.

With the rise of the Internet of Things (IoT), a huge market for so-called smart edge-devices is foreseen for millions of applications, like personalized healthcare and smart robotics. These devices have to bring smart computing directly where the data is generated, while coping with the limited energy budget. Conventional von-Neumann architecture fail to meet these requirements due to e.g., memory-processor data transfer bottleneck. Memristor-based computation-in-memory (CIM) has the potential to realize smart local computing for highly par­allel data-dominated AI applications by exploiting the inherent properties of the architecture and the physical characteristics of the memristors. This paper provides a broad overview of CIM architecture highlighting its potential and unique properties in enabling smart local computing. Moreover, it discusses design considerations of such architectures including both crossbar array as well as peripheral circuits; special attention is given to analog-to-digital converter (ADC), as it is the most critical unit of analog-based CIM operation e.g., vector-matrix multiplication (VMM). Finally, the paper outlines the potential future directions for CIM-based edge smart computing.

Quantum computers based on superconducting qubits have emerged as a leading candidate for a scalable quantum processor architecture. The core of a quantum processor consists of quantum devices that are manipulated using classical electronic circuits, which need to be co-designed for optimal performance and operation. As the principles governing the behavior of the classical circuits and the quantum devices are different, this presents a unique challenge in terms of the simulation, design and optimization of the joint system. A methodology is presented to transform the behavior of small-scale quantum processors to equivalent circuit models that are usable with classical circuits in a generic electrical simulator, enabling the detailed analysis of the impact of many important non-idealities. The methodology has specifically been employed to derive a circuit model of a superconducting qubit interacting with the quantized electromagnetic field of a superconducting resonator. Based on this technique, a comprehensive analysis of the qubit operation is performed, including the coherent control and readout of the qubit using electrical signals. Furthermore, the effect of several non-idealities in the system such as qubit relaxation, decoherence and leakage out of the computational subspace are captured, in contrast to previous works. As the presented method enables the co-simulation of the control electronics with the quantum system, it facilitates the design and optimization of near-term superconducting quantum processors.

Energy management in buildings equipped with renewable energy is vital for reducing electricity costs and maximizing occupant comfort. Despite several studies on the scheduling of appliances, a battery, and heating, ventilating, and air-conditioning (HVAC), there is a lack of a comprehensive and time-scalable approach that integrates predictive information such as renewable generation and thermal comfort. In this paper, we propose an online energy management framework to incorporate the optimal energy scheduling and prediction model of PV generation and thermal comfort by the model predictive control (MPC) approach. The energy management problem is formulated as coordinated three optimization problems covering a fast and slow time-scale.This reduces the time complexity without a significant negative impact on the global nature and quality of the result. Experimental results show that the proposed framework achieves optimal energy management that takes into account the trade-off between the electricity bill and thermal comfort.

In the past few years, novel fabrication schemes such as parallel and monolithic 3D integration have been proposed to keep sustaining the need for more powerful integrated circuits. By stacking several devices, wafers, or dies, the footprint, delay, and power can be decreased when compared to traditional 2D implementations. While parallel 3D does not enable very fine-grained vertical connections, monolithic 3D currently only offers a limited number of transistor tiers due to the high cost of the additional masks and processing steps, limiting the benefits of using the third dimension. In this paper, we introduce an innovative planar circuit netlist and layout approach, which enables a new 3D integration flow called 3D Nanofabric. The flow, consisting of $N$ identical vertical tiers, is aimed at single instruction multiple data processor Arithmetic Logic Units (ALUs). By using a single metal routing layer for each vertical tier, the process flow is significantly simplified since multiple vertical layers can potentially be patterned at once, similar to the 3D NAND flash process. In our study, we thoroughly investigate the layout constraints arising from the Nanofabric flow and the unique metal layer rule and propose several ways to overcome them. We then show that by stacking 32 layers to build a 32-bit ALU, the footprint is reduced by $8.7\times$ when compared to a conventional 7nm FinFET implementation.

As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory’s individual components contribute to the memory’s overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.

Electromigration (EM) is a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM models are either empirical or calibrated based on finite element analysis. Most of them consider only EM failures in the line without considering the via. Furthermore, the existing EM models do not model variations in the EM induced failure times, as typically observed in measurements. In this work, we develop a variation-aware EM analysis framework to model the bimodal failure distribution with early failures in via along with late failures in line. This EM model can be used for material and dimension exploration while being able to model and predict the variations in the bimodal EM failure distribution at various operating conditions.

Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory’s sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA’s cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads. The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier’s critical figure-of-merit, the offset voltage, with up to 26%.

Spin Transfer Torque Magnetic RAM (STT-MRAM) is being extensively considered as a promising replacement for Last Level Caches (LLC), due to its high density, low leakage and non-volatility. However, writes to STT-MRAM are energy intensive and have a high latency. While the high dynamic energy consumption during writes can be compensated by the low static energy consumption, the high latency results in performance degradation. This work shows that in contrast to SRAM-based LLCs, the performance degradation for STT-MRAM is primarily due to bank contention, when trying to satisfy a read request while the bank is being written. We holistically explore the effects of cache banking and cache contention on energy and performance in the LLC of mobile multicore systems, with in-order cores or with out-of-order cores. The detail of the analysis is enabled by highly accurate cache models, based on a 28nm SRAM industry compiler, and an in-house developed STT-MRAM compiler, which generates full STT-MRAM macro designs with silicon-validated MTJ stack and complete parasitic extraction at the 28nm node. Our results show that there is a clear difference in the energy-performance optimal banking configuration between STT-MRAM caches and SRAM caches. These low contention STT-MRAM cache designs with the optimal number of banks save at least 60% cache energy while losing at most single digit percentages in system performance compared to SRAM cache designs. This show an increased potential of using STT-MRAM as a replacement for SRAM in an LLC.

In the era of nanoelectronic circuits, temperature largely affects reliability and static power consumption of systems. In fact, temperature control in modern circuits is considered as a crucial system function, along with low-power operation. To this end, numerous thermal management approaches exist on the hardware, firmware and software layer. A widely used technique for that matter is dynamic voltage and frequency scaling (DVFS), aiming to control temperature by proper voltage and frequency decisions. CPU hot-plug is another technique brought from reliability and fault-tolerance domain that can be utilized for thermal management purposes. To this end, our work examines the thermal profile of an NXP IMX6Q board when different DVFS and CPU hot-plug actuations are applied. In addition, we move further and propose a synergy between the two methods while studying their effect on chip temperature, performance and energy consumption.

Heart activity can be monitored by means of ElectroCardioGram (ECG) measure which is widely used to detect heart diseases due to its non-invasive nature. Trained cardiologists can detect anomalies by visual inspecting recordings of the ECG signals. However, arrhythmias occur intermittently especially in early stages and therefore they can be missed in routine check recordings. We propose a hardware setup that enables the always-on monitoring of ECG signals into wearables. The system exploits a fully event-driven approach for carrying arrhythmia detection and classification employing a bio-inspired spiking neural network. The two staged Spiking Neural Network (SNN) topology comprises a recurrent network of spiking neurons whose output is classified by a cluster of Leaky integrate-and-fire (LIF) neurons that have been supervisely trained to distinguish 17 types of cardiac patterns. We introduce a method for compressing ECG signals into a stream of asynchronous digital events that are used to stimulate the recurrent SNN. Using ablative analysis, we demonstrate the impact of the recurrent SNN and we show an overall classification accuracy of 95% on the PhysioNet Arrhythmia Database provided by the Massachusetts Institute of Technology and Beth Israel Hospital (MIT/BIH). The proposed system has been implemented on an event-driven mixed-signal analog/digital neuromorphic processor. This work contributes to the realization of an energy-efficient, wearable, and accurate multi-class ECG classification system.

Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory’s digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over-or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. The existing EM models are mostly either based on empirical formulation or calibrated based on simulations using finite element analysis. Moreover, the existing models do not consider variations in material parameters causing variations in the EM induced failure times, as typically observed in measurements. In this work, we first calibrate a physics-based EM model using measured failure times of damascene copper at accelerated test conditions. We then extend the model to obtain the distribution of material parameters leading to observed variations in failure times. This model, being physics-based, can be used for material and dimension exploration while being able to model and predict the variations in the failure times at various operating conditions.

With the growing competition of utility-scale photovoltaic (PV) plants to provide electricity to the grid, accurate energy yield simulation is becoming essential. Apart from irradiance, forced convection can have an equally significant impact on solar cell temperature, which in turn affects the power output, hence the energy yield. As a consequence, the wind must be taken into account for an accurate estimation of PV installations' energy yield. However, no earlier studies have systematically investigated the impact of wind on precise energy yield simulation. In this study, we investigate how sensitive is PV module's output to forced convection. First, we reveal a significant deviation between the simulated PV module's energy yield and cell temperature compared to experimental results in case dynamic wind effects are neglected. Secondly, for controlled incremental forced convection with a steady state scenario, we show that for higher wind speed the change of PV module's cell temperature and power output is small with different forced convection. Whereas, for the low wind speed, small changes of forced convection imply a larger variation of the PV module's cell temperature and power output. This shows that for high wind speed region energy yield estimation is less sensitive on modelling errors. Whereas for the low wind speed region it is highly sensitive. This project has received funding from the European Union's Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No. 751159. Chowdhury, MG (corresponding author), Katholieke Univ Leuven, ELECTA ESAT MICAS, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium ; IMEC, Kapeldreef 75, B-3001 Heverlee, Belgium ; Imec Partner EnergyVille, Thor Pk 8320, B-3600 Genk, Belgium.

Despite advances in multicore smartphone technologies, battery consumption still remains one of customer’s least satisfying features. This is because existing energy saving techniques do not consider the electrochemical characteristics of batteries, which causes battery consumption to vary unpredictably, both within and across applications. Additionally, these techniques provide application specific fixed performance degradation in order to reduce energy consumption. Having a performance penalty, even when a battery is fully charged, adds to customer dissatisfaction. We propose a control-based approach for runtime power management of multicore smartphones, which scales the frequency of processing cores in response to the battery consumption, taking into account the electrochemical characteristics of a battery. The objective is to enable graceful performance modulation, which adapts with application and battery availability in a predictable manner, improving quality-of-userexperience. Our control approach is practically demonstrated on embedded Linux running on Cortex A15-based smartphone development platform from nvidia. A thorough validation with mobile and Java workloads demonstrate 2.9x improvement inbattery availability compared to state-of-the-art approaches.

Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.

Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%.)

Non-uniform operating conditions of photovoltaic modules have a huge impact on the energy generation of PV installations. To increase the energy yield of PV modules under non-uniform conditions, innovative module topologies have been proposed. However, a complete exploration of these topologies cannot be performed on the field, given the huge cost/time investment required for the realization of all potential topologies, as well as the large time required for comprehensively testing them in a real installation. Thus, it is more efficient and effective to compare them through simulations. An accurate and versatile simulation approach is proposed here which allows exploration of different PV module topologies under realistic time- and spatially-varying shading scenarios. The latter are created by matching measured weather data with simulated non-uniform and dynamic operating scenarios created by using the software SketchUp. The use of a physics-based bottom-up modeling approach for the different PV module topologies allows for accurate evaluation of the energy generated by each topology in the given operating conditions. Simulation results are presented that substantiate the feasibility of the methodology. Four relevant PV module topologies are compared, showing the better performance of reconfigurable topologies when uniform operating conditions are not dominant.

STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has attracted considerable attention of late since it is the most promising logic compatible nonvolatile memory that is suitable for advanced logic nodes (N28 and beyond) in terms of endurance, speed and power. Embedded STT-MRAM has thus been proposed as a candidate for emerging low standby-power connectivity systems such IoT (Internet-of-Things) and wearables. We utilize the high performance CoFeB based perpendicular MTJ (pMTJ) device to realize a low power and highly dense STT-MRAM array for such systems. This study is carried out on the TSMC 28nm technology node and includes a complete cross-layer design and analysis framework ranging from device modeling to circuit design, layout and system implementation. The process variations and temperature (PT) impact on the MTJ for the STT-MRAM design (and correspondingly the total energy consumption and performance of the system) is also analyzed. We report a ∼85% reduction in the energy consumption compared to the baseline SRAM based system for near negligible performance penalty (

To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ∼40% and ∼10%, respectively, depending on the stress conditions (temperature, voltage, workload).

Many modern applications exhibit dynamic behavior, which can be exploited for reduced energy consumption. We employ a two-phase combined design-time/run-time methodology that identifies different run-time situations and clusters similar behaviors into system scenarios. This methodology is integrated with our framework for system scenario based designs, which dynamically tune the hardware to match the application behavior. We achieve significant energy reductions for an extracted control structure of a video codec widely used in hand-held devices today. We encode a video stream consisting of different frame sizes based on measured available wireless bandwidth. Energy consumption is measured with a modified microcontroller board from Atmel with two alternative voltage and frequency settings. While maintaining the perceptual video quality and frame rate, our method results in up to 44% energy reduction for our encoded streams, even after including an average worst-case tuning overhead of 8.5%. In reality this overhead is typically negligible since the worst-case assumes very frequent tuning, while in realistic situations it will be performed at a much lower rate. This makes the expected gain over 50%.

This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-line swing (which reflect the degradation of the cell) and the sensing delay (which reflects the degradation of the sense-amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results show that in addition to the sense amplifier degradation, the cell degradation also contributes to the sensing delay increase; the share of this contribution depends on the cell design. Moreover, this sensing delay becomes worst at stressy workloads.

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three memory sense amplifier (SA) designs: low power (LP), mid power/performance (MP), and high performance (HP). As an evaluation metric, the sensing delay (SD) of the three designs is analyzed for various workloads using 45nm technology. The results show that HP SA degrades faster than MP SA and LP SA irrespective of the workload, supply voltage, and temperature. At nominal supply voltage and temperature, HP degrades up to 1.62x faster than MP, and up to 1.94x faster than LP designs for the worst case workload. In addition, the results show that an increase of 10% in power supply has a marginal impact on the relative degradation. In contrast, the results show that a temperature increment significantly worsens the BTI impact. Finally, the results show that for 16nm technology, BTI impact becomes worse and even causes read failures. This clearly indicates that designing for reliability is not only strongly application dependent, but also technology node dependent. Hence, one has to carefully consider the targeted application, design, and technology node in order to provide appropriate solutions.

With the down-scaling of CMOS technology into deep nano-scale era, negative-bias temperature instability (NBTI) effect becomes stochastic due to its widely distributed defect parameters. As a result, the delay degradation due to the intrinsic variability of NBTI becomes also stochastic and the matter is aggravated when it is combined with process variation. Accurate stochastic timing analysis of the circuit becomes very important in this case since over and under margining can lead to a significant performance or yield loss (timing failure), respectively. This paper proposes a flow and investigates the combined effect of stochastic NBTI and process variation on the performance of the VLSI design at the circuit level in a 7 nm FinFET technology node by abstracting atomistic NBTI models (for the stochastic behavior) to the circuit timing analysis flow.

An increasing number of High-Performance Applications demand some form of time predictability, in particular in scenarios where correctness depends on both performance and timing requirements, and the failure to meet either of them is critical. Consequently, a more predictable HPC system is required, particularly for an emerging class of adaptive real-time HPC applications. Here we present our runtime approach which produces the results in the predictable time with the minimized allocation of hardware resources. The paper describes the advantages in terms of execution time reliability and the trade-offs regarding power/energy consumption and temperature of the system compared with the current GNU/Linux governors.

Bias Temperature Instability (BTI) has become a major reliability challenge for nano-scaled devices. This paper presents BTI analysis for the SRAM write driver. Its evaluation metric, the write delay (WD), is analyzed for various supply voltages and temperatures for three technology nodes, i.e., 45nm, 32nm, and 22nm. The results show that as technology scales down, BTI impact on write delay (i.e., its average and +/− 3σ variations) increases; the 22nm design can degrade up to 1.9x more than the 45nm design at nominal operation conditions. In addition, the result shows that an increment in supply voltage (i.e., from −10% Vdd to +10% Vdd) increases the relative write delay during the operational lifetime. Furthermore, the results show that a temperature increment accelerates the BTI induced write delay significantly; while at 298K the degradation is up to 4.7%, it increases to 41.4% at 398K for the 22nm technology node.