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This paper presents the design of a 60GHz Quadrature Digitally-Controlled Oscillator for a low-power Frequency-Modulated Continuous Wave radar System-on-Chip. The accurate detection of vital signs requires 1 and Q demodulation of the received signal. The quadrature coupling is exploited to achieve a seamless and ultra wide frequency tuning range of 11 GHz. The oscillator is designed for integration in an All-Digital Phase-Locked Loop. The presented technique allows to simplify the interface with the digital loop filter without the need for an extensive calibration. A wide-band and low-power divider chain is designed as well using dynamic topologies. The circuits are integrated in GF 22-nm FDX CMOS technology and consume between 12.8 and 22.4 mW across the frequency range (17.6 mW on average) with a supply voltage of 0.8V.

This paper presents an analysis of different mod­ulations that can be used at low-IF in short-range frequency- modulated continuous wave (FMCW) radars which are more sensitive to DC offsets and flicker noise. These modulations are also a key functionality in multiple-input multiple-output (MIMO) FMCW radars to implement orthogonality between the different transmit signals. Architectures with two PLLs, set at slightly different frequencies to create a low-IF, and one PLL, using OOK and BPSK modulations, are compared regarding their phase noise at the resulting IF signal. Measurements were performed on a COTS 60 GHz FMCW radar to validate the calculated and simulated results.

This paper investigates the phase noise in LC oscillators with NMOS cross-coupled pair by means of a linear analysis. The latter includes the impact of noise sources that are often neglected, such as gate leakage shot noise, induced gate noise and all terminal access resistances noise. Despite not considering up-conversion of flicker noise, this linear analysis still provides reliable and useful results, demonstrated by means of a detailed comparison between the analytical description and simulations results from a 40nm and a 28nm CMOS technology.

This paper carries out a power-driven performance analysis on the most widely used LC oscillators' topologies, by means of the Inversion Coefficient methodology. The aim is to investigate on the best trade-off for Internet-of-Things related applications, where power consumption shall be minimized. The analysis is based on the BSIM6 model targeting a 40nm CMOS technology to investigate the trade-offs related to each topology and comparing them with respect to output voltage amplitude, phase noise and power consumption. The comparison is based on a figure-of-merit highlighting the best biasing regions, in terms of Inversion Coefficient, for the target required performance.