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Solid-state transformers (SSTs) are employing compact high-power medium-voltage (MV) medium-frequency transformers (MFTs) and enable the power transfer between galvanically isolated DC systems. Considering a typical SST isolation stage, i.e., a 166kW unregulated series-resonant DC-DC converter acting as a DC transformer (DCX) with equal input and output MV DC voltages of 7 kV (1:1-DCX), we derive component-level and system-level performance limits of air-cooled realizations with either an air-core transformer (ACT) or with a magnetic-core transformer (MCT). We describe the design of two fully rated MFT prototypes in detail and provide a comprehensive experimental characterization to validate the derived performance limits, including also the dielectric losses and the analysis of stray magnetic fields. The realized ACT and MCT prototypes achieve measured efficiencies of 99.5% and 99.7% at gravimetric power densities of 16.5 kW/kg and 6.7 kW/kg, respectively. Considering 10 kV SiC MOSFETs, calculated system-level efficiencies of the ACT-based and MCT-based 1:1-DCX result in 99.0% and 99.2% at the nominal operating point, with similar part-load efficiency characteristics. The paper concludes with an application-oriented qualitative evaluation of the two concepts. ISSN:2168-6777 ISSN:2168-6785

The control system of a phase-modular three-phase 10 kW / 230 V rms Ultra-High bandwidth series/parallel inter-leaved multi-level AC Power Source (UHPS) for P-HIL applications with 4.8 MHz effective switching frequency is optimized with respect to high bandwidth and low output impedance or output admittance (depending on whether output voltage or output current is controlled), by adding selected and effective enhancements to existing control structures. The theoretical findings are verified by means of a detailed simulation model, which also takes time-discretization effects arising from the FPGA-based digital control unit into account. The comparative evaluation of the investigated control structures reveals that the combination of capacitor current feedback, inductor voltage feed-forward, and reference prediction performs best for the control of both, output voltage and output current. In this regard, at 100 kHz and for operation with rated load resistance of 5.3 Ω, the phase-lag of the output voltage of the optimized voltage control system can be reduced from 19°, for the conventional two-loop control structure, to 7°; the small-signal bandwidth increases from 235 kHz to 427 kHz; and the output impedance at 100 kHz decreases from 0.6 Ω to 143 mΩ. In case of output current control, at an output frequency of 60 kHz, and for rated load resistance, the phase-lag of the output current can be reduced from 51° to 33°, for an optimized three-loop control structure, which is accompanied by an increase of the small-signal bandwidth from 63 kHz to 89 kHz and an increase of the output impedance from 11 Ω to 30 Ω at 60 kHz.

An accurate and fast transient calorimetric ferrite core-loss measurement method is proposed in this paper. In contrast to electrical measurements, the accuracy of the calorimetric approach is independent of the magnetic excitation and operating frequency. However, an accurate value of the thermal capacitance of the Core Under Test (CUT) is required, which can be achieved, e.g., by measuring the specific heat capacity of the measured core material using a Differential Scanning Calorimeter (DSC) or by using the CUT as a DC electric conductor and measuring its thermal response for known Joule heating. The proposed method is tested experimentally and compared successfully to a state-of-the-art electrical loss measurement method on MnZn ferrite cores.

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB and inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1% at an output power of P out = 640 mW and a switching frequency of f s = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at f s = 50 MHz and P out ∈ [500 mW, 600 mW]; at P out = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs., IEEE Open Journal of Power Electronics, 1, ISSN:2644-1314

This paper investigates implications of Low-Frequency (LF) phase current distortions that emanate from a grid-connected three-phase PFC rectifier, which powers a single-phase load inverter via a common DC-link. The presented study reveals the computation of the grid-side distortions that result for LF operation of the load inverter and determines the limits of the allowable distortion currents imposed by relevant standards (IEC 61000-3-11 and IEC 61000-3-12 with regard to harmonic currents and flicker, respectively). In the course of a design example, a PFC rectifier with a rated power of 20 kW and a DC-link voltage of 700 V is examined and it is found that, in case of a strong grid with an inner impedance of 21 m Ω, full compliance with IEC 61000 is achieved with a DC-link capacitance of 27 mF. However, in case of a weak grid with an assumed inner impedance of 212 m Ω, a very high DC-link capacitance exceeding 50 mF would be required. In this case, the presented design procedure is rather used to identify the frequency-dependent power limitation characteristic that enables the implementation of deratings in critical frequency ranges.

This paper introduces a special session on results of the Swiss competence center on energy research FURIES that has been established in coordination with the Swiss Energy strategy 2050 with the specific aim to develop, promote and deploy power grid-related innovative solutions toward the implementation of the Swiss Energy Strategy 2050. This contribution will report on activities within WP 3, “AC/DC multi-terminal grids and power electronics”. This WP includes three subtasks with contributions from the major Swiss technical universities: Multi-terminal HVDC system design, fault detection and clearing in multi-terminal HVDC, enabling component and converter technologies and applications. The spectrum of the center's activities is briefly introduced and as an illustrative example, the contributions of the SCCER FURIES in relation with HVDC grids are summarized. These contributions include: new high power DC testing methods and laboratories, new DC breaker principles and fault location techniques, AC/DC grid resonance analysis and novel converter technologies.

The recently presented Dual Three-Phase Active Bridge (D3AB) converter integrates a three-phase Power Factor Corrected (PFC) rectifier and a DC–DC converter stage with galvanic isolation, originating from the Dual Active Bridge converter, in a single converter unit, and accordingly features low complexity, high efficiency, and high power density. This paper proposes a multi-objective optimization procedure that considers the objectives of low RMS transformer currents and/or switching losses in order to identify Pareto-optimal low-loss modulation schemes for the D3AB rectifier that meet given specifications, prevent power pulsation, and facilitate interleaved operation. From the obtained results, which are verified by means of detailed circuit simulations, an improved modulation scheme is selected, which, compared to conventional modulation, reduces the primary-side switching losses by 54% and the total converter losses by 11%. Due to the general nature of the presented method, the application to other three-phase rectifier/inverter topologies is directly feasible.

Emerging applications, e.g., traction systems and utility scale renewable energy systems, demand for Medium Voltage (MV)power electronic switches with blocking capabilities above 20kV, which cannot be provided with today's 10kV or 15kV SiC power semiconductors. Therefore, this work investigates different concepts for the realization of a MV half-bridge, i.e., a series connection of 10kV SiC MOSFETs, a JFET Super Cascode arrangement, and Modular Multilevel Converter (MMCs)and Flying Capacitor Converter (FCCs)topologies. The FCC topology features several advantages such as reduced switching losses, reduced chip area, lower $\mathrm{d}v/\mathrm{d}t$ of the switching transitions, and robust voltage balancing. Moreover, the volume of the flying capacitors can be reduced with Quasi-2-Level (Q2L) operation of the half-bridge, where the intermediate voltage levels are only used during very short time intervals, i.e., during the switching transitions. This paper analyzes the design, the switching behavior, and the voltage balancing of the Q2L-FCC bridge-leg and confirms its suitability as a versatile MV switch. Finally, the integration of a complete bridge-leg, including gate drivers, isolated cooling interfaces, measurements, and Q2L control into a 300 kVA/40 kV SiC Super-Switch Intelligent Power Module (SiC-SS-IPM)is presented.

This work analyzes the properties of a new four-port, series-resonant, and bidirectional DC transformer topology in steady-state and transient conditions. The investigated topology evolves from the Integration of Three (3) Series-Resonant Converters (I3SRC), enables the realization of a converter with high efficiency (99.0%) and high power density (7.1 kW/dm3), due to the utilization of a three-phase High Frequency (HF) transformer and reduced capacitor currents in the secondary-side DC link, and features the use of a six-pack power module on the secondary side. The analysis is based on the results of detailed circuit simulations of an I3SRC, which takes the couplings between the phases, introduced by the three-phase transformer, into account and considers a DC transformer, i.e., DC-DC converter, with a total rated power of 15 kW, three primary-side DC voltages of 1.1 kV, and a secondary-side DC voltage of 700 V, which is a core part of a scaled demonstrator of a Solid-State Transformer (SST). The obtained findings clarify the self-stabilizing capabilities of the I3SRC for operation with Half-Cycle Discontinuous Conduction Mode (HC-DCM), even if the three isolated DC ports are subject to time-varying and substantially different power levels and different directions of energy transfer.

A new universal front-end PFC rectifier topology of a battery charger for Electric Vehicles (EVs) is proposed, which allows fast charging at rated and/or full power level in case of I-phase (USA) as well as 3-phase (Europe) mains supply. For a conventional 3-phase PFC rectifier, only 1/3 of the rated power would be available in case of I-phase operation. The new topology is based on a two-level six-switch (2LB6) 3-phase PFC rectifier, which is extended with a diode bridge-leg and additional windings of the Common-Mode (CM) chokes of the EMI filter. The focus of the paper is on the analysis of the generated CM and Differential Mode (DM) EMI noise for both operating modes, i.e., I-phase and 3-phase operation, resulting in guidelines for EMI filter design. The suggested topology modifications are also applied to a three-level T- type (Vienna) PFC rectifier structure. The theoretical considerations are verified with simulations. Finally, a 22kW prototype of the new universal PFC rectifier is designed using $\eta-\rho$ Pareto optimization, targeting an efficiency of 98.4 %, a power density of 6.8kW/dm3, i.e., a volume of 3.24dm3, and an EMI filter that ensures compliance with the CISPR class B EMI standard. Compared to a volume-optimized design of a conventional 3-phase topology of same power rating and efficiency, but limited 1-phase power transfer capability, the additional volume required for the proposed extension is less than 0.5dm3(15%) and therefore clearly justified considering the enabled universal applicability of the converter system.

This Paper proposes a novel Dual Three-Phase Active Bridge (D3AB) PFC rectifier topology for a 400 V dc distribution system, which features galvanic isolation, bidirectional power conversion capability, a high level of component integration, and can be dimensioned with respect to high efficiency. In the course of a comprehensive and in-depth analytical investigation, the working principle of the D3AB PFC rectifier is described in order to enable converter modelling and the derivation of mathematical expressions and limitations needed for converter design and optimization. The developed converter models are verified by means of circuit simulations. An overall optimization of a system with 400 V line-to-line input voltage, 400 V dc output, and P out = 8 kW rated power with respect to efficiency and power density reveals the feasibility of a full-load efficiency of 98.1% and a power density of 4 kW/dm3 if SiC MOSFETs are used. The finally presented design is found to achieve efficiencies greater than 98 % for P out > 1.7 kW.

With the availability of 10 kV SiC MOSFETs with low Zero Voltage Switching (ZVS) losses, Medium-Voltage (MV) converters, e.g., Solid-State Transformers (SST), capable of operation at very high switching frequencies become feasible. However, the optimization of MV and Medium-Frequency (MF) transformer of the dc–dc converter stage of a high power SST reveals that only limited improvements in efficiency and weight result for switching frequencies exceeding 50 kHz. Therefore, air-core transformers are expected to enable a realization with lower weight and, at the same time, simplified insulation coordination. This paper presents a comprehensive exploration of the design and performance spaces (efficiency, mass, volume) of a conventional, i.e., a magnetic-core based, and an air-core transformer employed in a resonant dc–dc converter with input and output voltages of 7 kV and a rated power of 166 kW. As a result, comparable efficiencies are achievable for both transformers (99.3% and 99.0%), but the SST with air-core transformer at a switching frequency of 103.6 kHz features 41% of the mass (10.3 kg) of a conventional transformer (24.9 kg at a switching frequency of 48.5 kHz). Accordingly, air-core transformers are of special interest for future weight-critical SST applications, e.g., in More Electric Aircraft and More Electric Ships.

This paper investigates the losses of a power inductor employed in a 2kW, 400V input DC-DC converter, in dependency of key operating parameters, i.e. switching frequency and current ripple. Based on detailed high-frequency winding and core loss models, including the implications of DC-bias, temperature and frequency on the core losses, and an analytic thermal model, a minimum loss inductor is designed for each combination of switching frequency, f, and current ripple, r. In the course of the optimization, the core (E55, N87) and the winding (litz wire, 100 μm) are considered given. Surprisingly, the evaluation of the losses calculated in the f-r domain reveals that nearly minimum inductor losses are obtained for a current ripple that is inversely proportional to the frequency, i.e., for a constant inductance. Further detailed investigations of the calculated inductor losses reveal a decrease of the losses for increasing frequencies up to a very high frequency of 500 kHz. In this regard, at f = 100kHz, minimum total losses of 4.0W result for r = 45%, which can be reduced to 1.8W at f = 500 kHz for r = 10%. Finally, the sensitivities of the losses with regard to different litz wires (71 μm, 200 μm) and a different core (E42, N87) are examined and a design guidance is extracted that summarizes the main findings of the detailed investigation. A calorimetric measurement set-up is used to measure the losses of a realized inductor at different operating points in order to confirm the theoretical considerations.

Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.

This paper details weight and efficiency analysis of a bidirectional ±270V dc to 3-phase 115V ac power electronic interface as part of an integrated modular power electronics cabinet, which supplies various loads, such as motors and ac buses from a HVDC bus in more electric aircraft. Through a case study the analysis shows that a significant reduction of filter component weight is achieved with a 3-level instead of a 2-level topology. The interactions and trade offs between the power electronic switched circuits and the EMI filter are analyzed and quantified. The potential benefits through the use of SiC-MOSFET's instead of Si-IGBTs and the implications for the circuit topologies are detailed. Recommendations for the choice of the optimal switched circuit topology, dependent on the importances of efficiency, weight, and reliability, are proposed. Furthermore, recommendations for the focus of future research enabling the competitiveness of the MEA concept is given.

The newly available Medium Voltage (MV) Silicon-Carbide (SiC) devices enable a great extension of the design space of MV inverters. This includes the utilization of unprecedented blocking voltages, higher switching frequencies, higher commutation speeds, and high temperature operation. However, all these factors considerably increase the insulation stress. This paper details the computation of dielectric losses, which are directly related to the insulation stress and can be used for the insulation design and diagnostic. After a review of the method used to compute dielectric losses, scalable analytical expressions are derived for the losses produced by PWM waveforms of DC-DC, DC-AC, and multilevel DC-AC inverters. Finally, a Medium-Frequency (MF) transformer is analyzed and the impacts of the insulation material and the operating temperature on the dielectric losses are discussed. It is found that the insulation losses can represent a significant share (17%) of the total transformer losses.

Solid-State Transformers (SSTs) are a promising technology since they combine a high efficiency with the integration of new functionalities and services in the grid. A SST establishes the interface between a MV AC three-phase grid and a LV AC or DC grid. For this reason a SST is subject to electrical stresses due to faults occurring in the grid. The MV and LV grids are in return exposed to failures of the SSTs. Therefore, a suitable design of the SST and its corresponding protection devices has to be found. This paper identifies the different stresses which are relevant for a SST, analyzes the protection mechanisms which are currently used for low-frequency transformers and proposes adapted protection schemes for SSTs. MV short circuits and overvoltages are identified as the most critical stresses and are analyzed in detail. Finally, some guidelines are extracted for designing a robust SST.

This work presents the modeling and the multi-objective optimization of a 2.5D inductor-based Fully Integrated Voltage Regulator (FIVR) with respect to efficiency η and/or chip area power density α, i.e. based on the η-α-Pareto-front, for microprocessor applications. The Voltage Regulator consists of a four-phase interleaved buck converter operated in Continuous Conduction Mode (CCM). The rated power of the considered converter is 1W, and input and output voltages are constant and equal to Vin = 1.7V and Vout = 0.85V. The optimization employs analytical models for the switches, which reside on chip and are manufactured in a 32nm CMOS SOI process, and for the passive components, i.e. racetrack inductors with magnetic core material and deep-trench capacitors that are fabricated in a silicon interposer. The optimization procedure considers thermal aspects and disregards solutions that lead to excessive component temperatures. According to the optimization results, either high efficiencies, greater than 90%, or high area power densities, with chip power densities greater than 20W/mm2 and interposer power densities higher than 1.5W/mm2 are achievable. The optimized design point, selected from the η-α-Pareto-front, features an efficiency of 90.1%, interposer power density of 0.309W/mm2, and a chip power density of 27.4W/mm2.

On-chip (or fully integrated) switched-capacitor (SC) voltage regulators (SCVR) have recently received a lot of attention due to their ease of monolithic integration [1-4]. The use of deep trench capacitors can lead to SCVR implementations that simultaneously achieve high efficiency, high power density, and fast response time [5]. For the application of granular power distribution of many-core microprocessor systems, the on-chip SCVR must maintain an output voltage above a certain minimum level U out, min in order for the microprocessor core to meet setup time requirements. Following a transient load change, the output voltage typically exhibits a droop due to parasitic inductances and resistances in the power distribution network. Therefore, the steady-state output voltage is kept high enough to ensure V OUT >V out, min at all times, thereby introducing an output voltage overhead that leads to increased system power consumption. The output voltage droop can be reduced by implementing fast regulation and a sufficient amount of on-chip decoupling capacitance. However, a large amount of on-chip decoupling capacitance is needed to significantly reduce the droop, and it becomes impractical to implement owing to the large chip area overhead required.

This paper details efficiency optimized operation and design of a bi-directional and isolated five-level Dual Active Bridge (5LDAB) converter for an application that requires ultra-wide voltage and power ranges. The rated power of the considered converter is 7.5kW, the specified input voltage range is 150V ≤ V dc1 ≤ 800V and the output voltage is constant, V dc2 = 700V. In order to achieve high efficiency levels in a wide operating range, a modulation scheme is proposed to minimize the transformer rms current. Results of transformer rms currents and of efficiencies are presented for the 5LDAB and compared with the results obtained for an efficiency optimized conventional Dual Active Bridge (DAB) converter. Compared with the DAB topology, the 5LDAB converter can achieve an overall reduction of transformer rms currents and of conduction losses in the higher voltage regime of the operating range.

In this paper, the η-ρ (efficiency - power density) Pareto front of a 20 kVA Uninterruptible Power Supply (UPS), comprising a Si and SiC hybrid 3-level T-type rectifier and inverter stage, and input / output side filters, is determined. A multi-objective optimization procedure is detailed, which employs an electrical converter model and coupled electro-thermal component models. Each component model determines the corresponding losses, volumes, and temperature rises. A detailed description of the inductor model is given which considers high frequency winding losses as well as core losses, and calculates the temperature rises inside the inductor, e.g. the hot-spot winding temperature. Based on the determined η-ρ Pareto front, the most suitable realization of the proposed UPS system is determined, which is based on the resulting sensitivities of the design parameters (switching frequency, current ripples, magnetic materials, etc.) on the performance of power converter system (efficiency and power density). As a result, a switching frequency of 16 kHz, maximum relative input and output side current ripples of 20%, amorphous core materials for DM inductors, and nanocrystalline core materials for CM inductors are selected in order to achieve a converter efficiency of 96.6% at a power density of 2.3 kVA/dm 3 .

On-chip switched capacitor (SC) converters for multicore microprocessor power delivery have the potential to reduce the overall energy consumption of future multicore microprocessor systems by independently regulating the voltage supply of each core. This paper describes an on-chip SC converter that can be reconfigured between a 2:1 and a 3:2 voltage conversion ratio to support a wide output voltage range from a single input supply. Regarding SC converter analysis and modeling, this paper extends an existing state space model framework to include the flying capacitors' parasitic bottom plate capacitors, which for on-chip SC converters significantly influence both the capacitor currents and the converter efficiency. A reconfigurable SC converter that supports an output voltage range of 700mV to 1150mV from a 1.8V input supply is implemented in a 32nm SOI CMOS technology that features the high-density deep trench capacitor. The converter achieves a maximum efficiency of 85.2% at 2.1W/mm2 power density in the 2:1 configuration and a maximum efficiency of 84.1% at 3.2W/mm2 in the 3:2 configuration.

For an on-chip or fully integrated microprocessor power-delivery system, the on-chip power converter must 1) be designed using the same technology as the microprocessor, 2) deliver high power density to supply a microprocessor core with small area overhead, 3) achieve high efficiency, and 4) perform fast regulation over a wide voltage range for dynamic voltage and frequency scaling (DVFS). On-chip switched-capacitor (SC) converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies [1-6].

A semi-analytical modulation scheme to operate a single-phase, single-stage dual active bridge (DAB) AC-DC converter under full-operating-range zero voltage switching (ZVS) is proposed. The converter topology consists of a DAB DC-DC converter, receiving a rectified AC line voltage via a synchronous rectifier. ZVS modulation strategies previously proposed in literature are either based on current-based (CB) or energy-based (EB) ZVS analyses. The combined phase-shift, duty-cycle, and switching frequency modulation proposed in this paper relies on a novel, current-dependent charge-based (CDCB) ZVS analysis, taking into account the commutation charge of the (parasitic) switch capacitances as well as the time dependency of the commutation currents. Thereby, commutation inductance is shown to be an essential element in achieving full-operating-range ZVS. Experimental results obtained from a 3.7 kW bidirectional electric vehicle battery charger which interfaces a 400 V DC-bus with the 230 Vac, 50 Hz utility grid are given to validate the analysis and practical feasibility of the proposed strategy.

This paper details the weight optimization of forced convection cooling systems, composed of a fan and an extruded-fin heat sink, required for a dc–dc converter of an airborne wind turbine system. The presented investigations detail the optimization of the heat sink's fins with respect to minimum weight and the selection of a suitable fan for minimum overall system weight. A new analytical cooling system model is introduced, and the calculated results are compared to the results determined with a preexisting analytical model and finite-element model simulations. The comparison to experimental results demonstrates the accuracy improvements achieved with the proposed methods. Compared to commercially available products, a weight reduction of 52% is achieved with the proposed optimization procedure for the required heat sink system with $R_{{\rm th},{\rm S}\hbox{-}{\rm a}}=1\ \hbox{K/W}$ .

For a Three-Level Three-phase T-type (3LTTC) rectifier and inverter of a high efficiency Uninterruptible Power Supply (UPS) with an output power of 20 kVA, most suitable semiconductor components are selected. For this purpose, this paper details conduction and switching loss models of T-type rectifiers and inverters, compares the total semiconductor losses achieved for RB-IGBTs and for different types of conventional IGBTs, and evaluates the improvements achieved if the Si rectifier diodes are replaced by SiC Schottky Barrier Diodes (SiC SBDs). The switching loss model is parameterized with measured switching losses. According to the results of this comparison, the rectifier preferably employs RB-IGBTs to realize the bi-directional switch and SiC SBDs for the rectifier diodes; switching frequencies up to 32.5 kHz are feasible for total semiconductor losses of the rectifier of 250W. For the inverter, a realization of the bi-directional switch using an anti-series connection of conventional IGBT/SiC SBD modules is found to be most suitable and facilitates a switching frequency of 19.7 kHz for maximum allowed losses of 250 W.

A common approach for selecting a suitable EMI filter is detailed based on the example of a realized single-phase 500W PFC rectifier. The presented work separates conducted EMI noise into Differential Mode (DM) and Common Mode (CM) components and derives expressions for the DM and CM insertion losses achieved if a given EMI filter is connected to a dedicated power converter. With the use of hardware measurement results it is shown that the impedances of the EMI filter and the PFC rectifier have a considerable impact on the realized insertion losses, which, at particular frequencies, may be even less than approximate worst-case estimations proposed in CISPR 17.

In solid-state-transformer technology, the isolation and power transfer between low voltage and medium voltage side is performed by a high power DC/DC converter. This DC/DC converter provides a defined ratio between input and output voltages, whereby, in order to reduce switching losses, zero-current-switching modulation schemes are often mandatory. The series-resonant-converter operated in half-cycle discontinuous-conduction-mode possesses all the aforementioned features, thus making it highly attractive for solid-state-transformer applications. For this reason, a comprehensive analytical model of the converter's static and dynamic behavior is provided in this paper. In addition, a method to model the switching losses under ZCS conditions, which is based on the behavior of the stored charge in the semiconductors, is presented. This enables an efficiency/power density (η-ρ) Pareto optimization of the aforementioned converter system.

The design procedure for a bidirectional DAB dc-dc converter, which provides a high dc voltage of 8kV to the tether of a 100 kW Airborne Wind Turbine (AWT) system, is presented. The maximum allowed weight of the dc-dc converter is 25 kg and, thus, the main challenge is the realization of a light-weight DAB converter. The investigated dc-dc converter is split up into 16 single DAB modules with a rated power of 6.25 kW and a dc port voltage of 2kV. Thus, a weight of less than 25 kg/16 = 1.56 kg needs to be achieved for a single DAB module. The design method used to obtain the minimum weight DAB converter, based on the evaluation of a power-to-weight ratio versus efficiency Pareto Front γ-η-Pareto Front) is presented in this paper. For this purpose the transient voltages and currents of the employed SiC JFETs during switching are discussed in detail, since the respective measurement results allow for a prediction of the switching losses. Moreover, the calculated transformer is realized and experimental results are used to verify the weight, the losses, and the cooling system performance of the transformer. For a single DAB module a weight of m = 1.43 kg, an efficiency of η = 97%, and a power-to-weight ratio of γ = 4.4kW/kg results.

For realizing bidirectional and isolated AC/DC converters, soft-switching techniques/topologies seem to be a favourable choice as they enable a further loss and volume reduction of the system. Contrary to the traditional dual-stage approach, using a power factor corrector (PFC) stage in series with a DC/DC isolation stage, we showed recently that the same functionality can be achieved under full soft-switching operation using a single-stage dual active bridge (DAB) AC/DC converter. This paper investigates the performance of this single-stage approach by comparing it with a state-of-the-art conventional dual-stage concept (both soft-switching converters), where a bidirectional interleaved triangular current mode (TCM) PFC rectifier was chosen in combination with a DAB DC/DC converter. The advantages and drawbacks of each concept are discussed in detail, focusing on the impact of the utilized semiconductor technology and silicon area on the converter efficiency. Furthermore, a comprehensive comparison of power density is allowed by the analytical models that correlate the component losses with their respective volume.

For Voltage Regulator Modules (VRM), integrating the power converter with the load in an advanced integration process is a method to deliver power at higher voltage levels, and thereby overcome the high supply current requirements predicted by the 2009 International Technology Roadmap for Semiconductors (ITRS). The most conventional converter type used is the buck or step-down converter. For this converter, the output inductor is recognized as the performance limiting component with respect to efficiency and area requirements. This paper details an inductor optimization procedure for Power Supply in Package (PSiP) and Power Supply on Chip (PwrSoC) applications. Targeting the highest possible efficiency for a specified area-related power density, the optimization procedure determines the best inductor dimensions given the buck converter operating conditions. The optimization procedure is verified using experimental data obtained from a PCB inductor realization. According to the results, the most favorable inductor achieves an efficiency of 94.5% and an area-related power density of 1.97W/mm2 at a switching frequency of 170MHz.

Airborne Wind Turbines (AWT) represent a radically new and fascinating concept for future harnessing of wind power. This concept consists of realizing only the blades of a conventional wind turbine (CWT) in the form of a power kite flying at high speed perpendicular to the wind. On the kite are mounted a turbine, an electrical generator and a power electronics converter. The electric power generated is transmitted via a medium voltage cable to the ground. Because of the high flight speed of the power kite, several times the actual wind speed, only a very small swept area of the turbine is required according to Betz's Law and/or a turbine of low weight for the generation of a given electric power. Moreover, because of the high turbine rotational speed, no gear transmission is necessary and the size of the generator is also reduced. For takeoff and landing of the power kite, the turbines act as propellers and the generators as motors, i.e. electric power is supplied so that the system can be maneuvered like a helicopter. In the present work the configuration of power electronics converters for the implementation of a 100kW AWT is considered. The major aspect here is the trade-off between power-to-weight ratio (W/kg) and efficiency. The dependence of cable weight and cable losses on the voltage level of power transmission is investigated, and a comparison made of low voltage (LV) and medium voltage (MV) versions of generators. Furthermore, the interdependence of the weight and efficiency of a bidirectional Dual Active Bridge dc-dc converter for coupling the rectified output voltage of a LV generator to the MV cable is discussed. Based on this, the concept offering the best possible compromise of weight and efficiency in the power electronics system is selected and a model of the control behavior is derived for both power flow directions. A control structure is then proposed and dimensioned. Furthermore, questions of electromagnetic compatibility and electrical safety are treated. In conclusion, the essential results of the work are summarized and an outlook on future research is given. To enable the reader to make simplified calculations and a comparison of a CWT with an AWT, the aerodynamic fundamentals of both systems are summarized in highly simplified form in an Appendix, and numerical values are given for the 100kW system discussed in this work.

In future applications, e.g. in ultra-flat OLED lamp drivers or flat screen power supplies, ultra-flat power systems are highly demanded. Therefore, the design and implementation of a PCB-integrated flyback transformer for a 1 mm thin PFC rectifier is under investigation. In this paper, an overview on several integration methods is given. It is shown that the PCB-integration of magnetic cores results in the required thickness of 1 mm and in a high energy density. Therefore, the design and the realization of ultra-flat magnetic components with PCB-integrated cores is detailed in this paper. The presented multi-objective design procedure determines the inductor and/or transformer setup optimal with respect to minimal losses and/or minimal footprint; for this purpose, the proposed design procedure considers all required electrical, magnetical, and geometrical parameters of the magnetic component. Furthermore, the design procedure accounts for anisotropic core loss behavior and includes an accurate reluctance model. Experimental results are used to verify the design procedure.

In this paper, an innovative DC-DC converter is investigated which provides electrical power to the gate driver units of medium voltage level converters. For the discussed DC-DC converter, a galvanic isolation (isolation voltages of up to 35 kV) is required. This electrical isolation is achieved with a coreless transformer in order to obtain a cost-effective solution. Furthermore, the DC-DC converter contains a full-bridge converter being operated with low switching losses, a resonant compensation network to achieve a high overall efficiency and an output side rectifier. In this paper, the design of the coreless transformer, the appropriate compensation networks and the power electronics are discussed in detail. Moreover, measurement results obtained from a 100 W prototype, operated at a switching frequency of 410 kHz, are presented. With the proposed setup, a high overall efficiency of up to 80% and a transformer breakdown voltage of 55 kVrms is achieved. Thus, the proposed converter concept represents a very competitive solution with respect to the typically employed DC-DC converters with dry-type cast coil transformers.

The derivation of an accurate small-signal model for a galvanically isolated, bidirectional DC-DC converter and the implementation of a corresponding controller on a digital signal processor (DSP) as well as key methods and functions required for the digital implementation are detailed in this paper. The investigated DC-DC converter, an automotive Dual Active Bridge (DAB) system enables power transfer between a low voltage port (ranging from 11 V to 16 V) and a high voltage port (240 V to 450 V). The nominal power rating is 2 kW. The developed small-signal model yields highly accurate results for the DAB system, but the proposed modelling procedure could also be applied to arbitrary resonant power converters with unidirectional or bidirectional power transfer.

The main aim of this paper is to improve the performance of high current dual active bridge converters when operated over a wide voltage range. A typical application is for fuel cell vehicles where a bi-directional interface between a 12V battery and a high voltage DC bus is required. The battery side voltage ranges from 11V to 16V while the fuel cell is operated between 220V and 447V and the required power is typically 1kW. Careful analysis shows that the high currents on the battery side cause significant design issues in order to obtain a high efficiency. The standard phase shift modulation method can result in high conduction and switching losses. This paper proposes a combined triangular and trapezoidal modulation method to reduce losses over the wide operating range. Approximately, a 2% improvement in efficiency can be expected. An experimental system is used to verify the improved performance of the dual active bridge using the proposed advanced modulation method.

The working principles and design equations of four different isolated, bi-directional DC to DC converter topologies (a dual active bridge converter, a series resonant converter and two multiple stage topologies) for a 2 kW bi-directional battery charger that can be operated in a wide input and output voltage range are presented in this paper. The results of a detailed mathematical analysis of the converter topologies as well as digital simulation results are used to select the most efficient topology for this specific converter application, where the two-stage series resonant converter is identified to be the most promising, with up to 90% efficiency at rated power.