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Demand for Internet of Things (IoT) devices has generated interest in fault-tolerant address decoders. Address decoders affect the energy required to establish a data link and monitor a wireless channel through metrics such as detection probability and false alarm probability. This brief establishes a framework for calculating detection and false alarm probabilities and shows that limiting the number of correctable errors eliminates simultaneous false alarms, reduces the probability of false alarm, and reduces the maximum normalized power consumption of a sleep node due to false alarms by 16.9 dB. The probability expressions are formulated so that the detection probability, the false alarm probability, the energy to transmit, and the power to monitor a channel can be adjusted digitally, yielding a counter-based implementation that reduces the energy consumption of the address decoder to 1.3 pJ/bit for a data rate of 200 bps in $0.18~\mu \text{m}$ CMOS. [ABSTRACT FROM AUTHOR]

Designing high-speed and low-power interconnects is a challenge for high performance computing applications, while silicon photonics can provide attractive solutions to perform high-density communications. This paper presents an electro-optic transmitter operating at 20 Gbps (gigabit per second), as a first step toward the demonstration of chip-to-chip optical links. The architecture is based on a dual-drive Mach-Zehnder interferometer co-integrated with a 55-nm CMOS driver. Design optimizations and trade-offs analysis enable low-energy and negligible bit error rate ($BER < 10^{-12}$) transmission at 20 Gbps, by exploring a firstly reported low extinction ratio (ER) modulator. A wire-bonding board assembly is then carried out to co-integrate hybrid transmitter. Co-simulations are presented and show good agreement with experiments. Combined with an adequate MZM bias, this solution achieves a minimal energy consumption of 0.9 pJ/bit while ensuring a sufficiently large ER of 0.73 dB for chip-to-chip interconnects applications. [ABSTRACT FROM AUTHOR]

Small geometry effects have become increasingly important in analog circuits as transistors continue to shrink. As a result, transconductance-to-drain current (${g_{m}/I_{D}}$) transistor parameters are no longer width-independent. In this brief, a procedure to develop “unit-sized” transistors with minimal sensitivity to small geometry effects is proposed. It is shown that by using the unit-sized transistors, the impact of small geometry effects on ${g_{m}/I_{D}}$ dependent parameters such as current density and self gain can be reduced to 3.6% and 1.5%, respectively. [ABSTRACT FROM AUTHOR]

Noise optimization is a challenging problem for nanoscale metal–oxide–silicon field-effect transistor circuits. This brief presents a technique that uses transconductance-to-drain current (gm/ID)-dependent transistor-noise parameters to explore the design space and to evaluate tradeoff decisions. An expression for the corner frequency of the folded-cascode amplifier is derived. The design process demonstrated in this brief using the folded-cascode amplifier is applicable to a wide class of amplifier circuits. [ABSTRACT FROM AUTHOR]