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The Mean Teacher (MT) model of Tarvainen and Valpola has shown favorable performance on several semi-supervised benchmark datasets. MT maintains a teacher model's weights as the exponential moving average of a student model's weights and minimizes the divergence between their probability predictions under diverse perturbations of the inputs. However, MT is known to suffer from confirmation bias, that is, reinforcing incorrect teacher model predictions. In this work, we propose a simple yet effective method called Local Clustering (LC) to mitigate the effect of confirmation bias. In MT, each data point is considered independent of other points during training; however, data points are likely to be close to each other in feature space if they share similar features. Motivated by this, we cluster data points locally by minimizing the pairwise distance between neighboring data points in feature space. Combined with a standard classification cross-entropy objective on labeled data points, the misclassified unlabeled data points are pulled towards high-density regions of their correct class with the help of their neighbors, thus improving model performance. We demonstrate on semi-supervised benchmark datasets SVHN and CIFAR-10 that adding our LC loss to MT yields significant improvements compared to MT and performance comparable to the state of the art in semi-supervised learning., Comment: 8 pages, 7 figures

Anomaly detection on large scale spatio-temporal data such as climate data is a challenging task depending on the spatial and temporal resolution and autocorrelation of the data. When considering global gridded daily temperature data, the number of locations and the length of time period considered makes anomaly detection a big data problem. Gaussian Process (GP) Learning is a method that is well-suited to identify the complex spatial and temporal autocorrelation properties of spatio-temporal data. One of the primary challenges with using GP is the computational complexity associated with inverting a covariance matrix. This is further compounded when considering data on a national/global scale and performing anomaly detection using such methods often requires dedicated high performance computing platforms. In this paper, we describe a purely temporal scalable anomaly detection technique for gridded temperature data based on GP Learning that ignore the spatial autocorrelation between neighboring grids and perform anomaly detection on each of the grids in parallel, thereby reducing the execution time. We introduce three methods: a standalone data parallel approach using a single GPU, a distributed memory version on multi-node clusters using MPI, and a mixed parallel approach using multiple GPUs. In comparison to a sequential approach, they are 17.2x, 47.1x, and 88.9x faster, respectively.

Light Detection and Ranging (LIDAR) applications pose extremely challenging dynamic range (DR) requirements on optical time-of-flight (ToF) receivers due to laser returns affected by the inverse square law over 2-3 decades of distance, diverse target reflectivity, and high solar background [1]. Integrated CMOS SPADs have a native DR exceeding 140dB, typically extending from the noise floor of few cps to 100’s Mcps peak rate. To deliver this DR to downstream DSP, large SPAD time-resolved imaging arrays must count and time billions of single photon events per second demanding massively parallel on-chip pixel processing to achieve practical I/O power consumption and data rates. Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high-fill-factor SPADs optimised for NIR stacked on dense nanoscale digital processors [2]. Stacked sensor architectures involving pixel-level histogramming, on-chip peak detection and TDC/processor resource sharing are now being investigated [3–5].

III-nitride laser diodes (LDs) are promising sources for light fidelity (LiFi) networks, underwater wireless optical communications (UWOC), and plastic optical fiber (POF) communications [1] due to their high modulation bandwidths ($\gt 5$GHz) compared to LEDs ($\lt 20$ MHz). Their narrow linewidths also enable robust free-space Gb/s LiFi links in the presence of high intensities of sunlight through selective spectral filtering. Fully integrated CMOS visible light communications (VLC) receivers have recently been developed to enable miniaturised and low cost Gb/s LD-based links [2]. Sensitivity of these devices is constrained by electrical noise sources such as thermal, shot or excess noise related to the employment of PIN photodiodes (PDs) or linear avalanche photodiodes (APDs) and their amplification circuits. The extremely high gain of SPADs operating in Geiger mode allows quantum sensitivity limits to be approached [3], [4]. A SPAD receiver (RX) for fiber optic applications achieved 200Mb/s at $6.5\times 10 ^{-3}$ BER within 24dB of the quantum limit [3]. In this paper, we demonstrate a fully integrated CMOS SPAD RX SoC extending this data rate by $2.5 \times $to 500Mb/s, whilst improving sensitivity to -46.1dBm, reducing the margin to the quantum limit to only 15dB. Our RX architecture permits massively parallel (4096) photon event summation to be achieved at a high fill-factor (43%) and sample rate (800MHz). Detector redundancy obviates the requirement on current RX implementations that the SPAD dead time be matched to the symbol period to achieve the maximum data rate [3, 4, 5]. Another advantage is that complex modulation schemes such as OFDM or PAM can be applied for high spectral efficiency and multipath interference mitigation. We demonstrate the RX in a practical, background insensitive VLC link at 1m in 1klx ambient conditions using a 450nm LD. The higher power consumption and dead time pile-up nonlinearity of the SPADs at high signal levels, leads us to conclude that the practical use of this device to be in assistance (rather than replacement) of existing APD or PIN RXs for LiFi, UWOC and POF applications towards extended link range or maintaining a low rate link in highly scattering environments.

Direct time of flight (TOF) pixels implemented with single photon avalanche diodes (SPADs) are the most suitable candidates for high sensitivity and picosecond timing resolution TOF sensors. However, their performance is severely limited in high dynamic range (HDR) applications such as advanced driver assistance systems (ADAS) and gesture recognition. Sampling the full dynamic range of the SPAD detector requires high bit-depth counters which until now has resulted in large pixel area and low fill-factor (FF). We present a SPAD-based tOf pixel in 40nm CMOS achieving the highest dynamic range over the state of the art. Dual time-gate sampling with two in-pixel 14-bit ripple counters achieves a counter-limited dynamic range of 84dB. The dynamic range of the pixel can be further extended by chaining the counters sampling with one time-gate to reach the intrinsic SPAD dynamic range limit of 119dB in a single exposure. The pixel has a 40pm × 20pm pitch and 16% FF. It generates 7 selectable sub-nanosecond time-gates down to 330ps with differential nonlinearity (DNL) smaller than 1 % of the time-gate width and a total temporal range tunable between 1.65ns to 40ns.

A 256×256 Single Photon Avalanche Diode (SPAD) image sensor operating at 100kfps with fill factor of 61% and pixel pitch of 16μm is reported. An all-NMOS 7T pixel allows high uniformity gated operation down to 4ns and ∼600ps fall time with on-chip delay generation. The sensor operates with 0.996 temporal aperture ratio (TAR) in rolling shutter and has a parasitic light sensitivity (PLS) in excess of −160dB when operated in global shutter. Gating and cooling allow the suppression of dark noise, which, in combination with the high fill factor, enables competitive low-light performance with electron multiplying CCDs (EMCCDs) whilst offering time-resolved imaging modes.

We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

We investigate the field-effect control of ions in nanofluidic transistors (NFTs) with characteristic channel size (∼100 nm) significantly larger than the system's Debye Length (∼10 nm). These 100 nm NFTs achieve an ionic current modulation ratio of ∼2.5, demonstrating better performance than the state-of-the-art 20 nm NFTs. The result attests a new operating regime beyond the Debye-screening limit. The relaxed constraint on channel size offers advantages in device manufacturing, testing, and reliability. It also opens up new applications in biological sensing and sample preparation.

This paper studies complex modulation schemes,including orthogonal frequency-division multiplexing (OFDM),received by a single photon avalanche diode (SPAD) arrayintegrated circuit (IC). A SPAD operates in the Geiger mode,and is able to detect single photons. This feature enables orderof magnitude receiver sensitivity in intensity modulation (IM)/ direct detection (DD) Visible Light Communication (VLC)systems. The tradeoff between received power and bit error ratio(BER) using both pulse-amplitude modulation (PAM) and OFDMis shown. A first order model of the noise in a digital SPADreceiver is derived. The noise in the experimental receiver chipapproaches the predicted noise in our model, and we achievereceiver sensitivity of −64 dBm with a 100 kbit/s signal at aBER of 10−5. It is concluded that future improvements in SPADVLC receiver architecture will allow sensitivity to approach thequantum limit.

We show reception of a higher order modulation scheme using a novel high-fill-factor XOR-tree based digital silicon photomultiplier array. We also demonstrate and model even-order XOR cancellation and nonlinear saturation resulting from this design.

The conditions for a quantum measurement to discriminate a set of states with the minimum probability of error were specified by Yuen, Kennedy and Lax, and are often termed the YKL conditions [1]. Since light is quantum mechanical, the ultimate limit on minimum-error discrimination of an optical modulation constellation is determined by the YKL bound. Standard optical receivers (i.e., direct, homodyne or heterodyne detection)—even at their respective ideal operation limits—cannot achieve this performance. Recently, it was shown that a ‘sequential waveform nulling’ (SWN) receiver can, not only discriminate an arbitrary M-ary coherent-state (ideal laser-light) constellation asymptotically at the YKL bound in the high-power limit, but that it achieves a factor of 4 better in the asymptotic error-probability exponent compared with heterodyne detection—the only conventional optical receiver that can in principle be employed for detecting an arbitrary phase-and-amplitude modulated constellation [2]. The SWN receiver can be built with standard optical components; i.e., beamsplitters, local-oscillator lasers, delay loops and single-photon detectors. However on the other hand, in the high power regime, heterodyne detection is known to achieve a reliable communication rate that asymptotically approaches the Holevo capacity of a lossy-noisy optical channel (the ultimate limit to the classical capacity of a quantum channel) [3]. In fact, in the high power regime, heterodyne detection was also shown recently to achieve the optimal second-order coding rate, when using the optimal (Gaussian) input distribution [4]. In this paper, we show that when restricted to the M-ary phase-shift keying (PSK) ensemble, that the SWN receiver's superiority over heterodyne detection in its asymptotic error exponent of the demodulation error probability, translates to a slightly higher capacity and a pronouncedly higher finite blocklength reliable-communication rate. We also quantify, via a numerical calculation, the dependence of the SWN receiver's capacity on the order in which the PSK constellation points are nulled. Our results suggest that for short-latency PSK-modulated optical communication in the high spectral efficiency regime—for which heterodyne detection is the conventional receiver choice—that it may be beneficial to employ the SWN receiver, despite the widely-regarded capacity optimality of heterodyne detection in this operating regime.

Time-correlated single photon counting (TCSPC) is a photon-efficient technique to record ultra-fast optical waveforms found in numerous applications such as time-of-flight (ToF) range measurement (LIDAR) [1], ToF 3D imaging [2], scanning optical microscopy [3], diffuse optical tomography (DOT) and Raman sensing [4]. Typical instrumentation consists of a pulsed laser source, a discrete detector such as an avalanche photodiode (APD) or photomultiplier tube (PMT), time-to-digital converter (TDC) card and a FPGA or PC to assemble and compute histograms of photon time stamps. Cost and size restrict the number of channels of TCSPC hardware. Having few detection and conversion channels, the technique is limited to processing optical waveforms with low intensity, with less than one returned photon per laser pulse, to avoid pile-up distortion [4]. However, many ultra-fast optical waveforms exhibit high dynamic range in the number of photons emitted per laser pulse. Examples are signals observed at close range in ToF with multiple reflections, diffuse reflected photons in DOT or local variations in fluorescent dye concentration in microscopy. This paper provides a single integrated chip that reduces conventional TCSPC pile-up mechanisms by an order of magnitude through ultra-parallel realizations of both photon detection and time-resolving hardware. A TDC architecture is presented which combines the two step iterated TCSPC process of time-code generation, followed by memory lookup, increment and write, into one parallel direct-to-histogram conversion. The sensor achieves 71.4ps resolution, over 18.85ns dynamic range, with 14GS/s throughput. The sensor can process 1.7Gphoton/s and generate 21k histograms/s (with 4.6μs readout time), each capturing a total of 1.7kphotons in a 1μs exposure.

A 9:8 µm pitch SPAD-based pixel is presented with a novel and scalable Sample and Hold (S/H) Time to Amplitude Converter (TAC) pixel architecture offering the potential to create high spatial resolution Time Correlated Single Photon Counting (TCSPC) image sensors in the future. This pixel pitch is an order of magnitude smaller than previous TCSPC pixels. The NMOS-only TAC performance is measured in a single point TCSPC optical experimental setup. 93ps LSB time resolution is obtained over 80ns dynamic range. Dynamic range limitations are discussed and improvements are suggested. Index Terms—SPAD, Single Photon Avalanche Diode, TAC, Time to Amplitude Converter, TCSPC, Time Corre- lated Single Photon Counting.

The file attached to this record is the author's final peer reviewed version. The Publisher's final version can be found by following the DOI link. Existing assistive living and prompting based solutions have adopted a relatively complex approach to supporting individuals. These solutions have involved sensor based monitoring, activity recognition and assistance provisioning. Traditionally they have suffered from a number of issues rooted in scalability and performance levels associated with the activity recognition process. This paper introduces a simplistic approach to assistive living within a user's residence through the use of NFC tags and smart devices. The core concept of this approach is presented and is subsequently placed within the context of related work. A description of the architecture is provided and results following technical evaluation of the first system prototype are discussed.

A 320×240 single photon avalanche diode (SPAD) based single photon counting image sensor is implemented in 0.13μm imaging CMOS with state of the art 8μm pixel pitch at 26.8% fill factor. The imager is demonstrated operating as a global shutter (GS) oversampled binary image sensor reading out at 5.14kFPS. Frames are accumulated in real time on FPGA to construct a 256 photon/8bit output image at 20FPS.

By increasing the strength of the negative dielectrophoresis (DEP) force, we demonstrate a significantly improved electrokinetic actuation and filtering microsystem. A pinhole-free, nanometer-scale, thin film oxide was deposited using atomic layer deposition, as a protective layer to protect the electrodes from corrosion, when applying high AC voltages (>20 Vpp) at the electrodes. The electrodes were capacitively coupled to the electrolyte buffer by the application of a high frequency AC voltage signal, thus avoiding electric field degradation and the consequent reduction in dielectrophoresis force due to the presence of the insulating oxide layer. In this work, we demonstrated the use of this DEP-enhanced device for two microfluidic applications. First, we demonstrate an on-chip platform for the depletion of cells and highly abundant serum proteins in blood, which is a prerequisite to assay low-abundance protein biomarkers. For the second application, we show 100% detachment of anti-IgG and IgG bound beads (which is on the same order of magnitude in strength as typical antibody-antigen interactions) from the surface, upon the application of the enhanced negative DEP force. This capability offers the possibility of performing a bead-based multiplexed assay against multiple antigen targets where in a single microfluidic channel various regions are immobilized with a different antibody, each targeting a different antigen.

This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial processor running realistic applications. Dependencies of aging effects on switching-activity and power-state of workloads are quantified. This paper presents an “instance-based” simulation flow, which creates a standard-cell library for each use of the cell in the design, by aging each transistor individually. Implementation results show that processor timing degradation can vary from 2% to 11%, depending on workload. Lifetime computational power efficiency improvements of optimized self-tuning is demonstrated, relative to a one-time worst-case guardbanding approach.

This paper presents a novel algorithm: Verfied Partial Object Detector (VPOD) for accurate detection of partially occluded objects such as furniture in 3D point clouds. VPOD is implemented and validated on real sensor data obtained by our robot. It extends Viewpoint Feature Histograms (VFH), which classify unoccluded objects, to also classify partially occluded objects such as furniture that might be seen in typical office environments. To achieve this result, VPOD employs two strategies. First, object models are segmented and the object database is extended to include partial models. Second, once a matching partial object is detected, the complete object model is aligned back into the scene and verified for consistency with the point cloud data. Overall, our approach increases the number of objects found and substantially reduces false positives due to the verification process.

This paper studies how social relationships are reshaped by the enactment of ICTs through the interplay of traditional and new actors. Building on the perspectives of an ecology of games and the sociology of translation, we propose a framework to study cross-organizational processes and technology-enabled reconfigurations of power and resources of the interrelated actors. We then illustrate the framework with the case of residential Internet infrastructure development taking place in a developing country context. The proposed framework is helpful to capture the complexity and unpredictability of cross-organizational interactions of the actors embedded in the mesh up of traditional and new actors embedded in the broader context of social, economic and power processes.

By making use of the advantages offered by micro and nanotechnologies, we aim to develop technologies which will decrease cost, increase assay speed, and improve limit of detection in biomolecular assays. Increasing sensitivity can enable earlier detection, and also can allow for identification of low-abundance markers that are not detectable with current techniques. We have previously developed a microfluidic platform capable of detecting enzyme activity at the attomolar level [1]. In order to transform this technology into a high throughput multiplexed assay, while maintaining low cost, instead of using microfluidic valves which requires extensive tubing and external pumps, it is desirable to achieve fluidic control of microparticles electrically. Using modern VLSI techniques, routing of hundreds or even thousands of electrodes and interconnects on a silicon chip is trivial compared to the requirement of connecting hundreds of tubes to a fluidic chip, which can become a plumbers nightmare.

We investigate DNA passage through a nanofluidic transistor (NFT) composed of large diameter nanopores (~200nm) with an embedded metal gate. The nanopores are large enough to be made by currently available photolithography process for manufacturability. We observe that the NFT is capable of electrostatic control of DNA capture rate, the equivalent of current in the electron transistor, with similar operating principle as their electron device counterpart.

Random telegraph noise (RTN) in high-κ nMOSFETs is directly linked to Positive Bias Temperature Instability (PBTI). For the first time, the correlation between I d - and I g -RTN is clearly observed in high-κ MOSFET. I g -RTN is directly related to physical trapping or de-trapping and the I d -RTN reflects sensitivity to charge trapping as determined by gm, which is confirmed by both experiments and TCAD simulations.

Coupled Poisson-Nernst-Planck and Stokes simulations demonstrate the operating principles of using electrical biases in dual-gated nano-fluidic channels to create localized and tunable solution zones of either depleted or accumulated ions. Scaling studies reveal that such ion modulations overcome the limit of counter-ion screening and remain effective even for channel widths greatly exceeding the Debye screening length. The underlying mechanism is attributed to the transport-induced de-screening of gating potentials.

Today's design of avionics is being pulled in two opposite directions — increased use of COTS and more requirements for certification. In particular, graphics processing has largely relied upon COTS devices even though the need for certification of GPUs has been amplified. This paper provides a background on graphics processing, summarizes the avionics requirements, surveys the options for graphics processing in avionics, and presents an architecture for an FPGA-based graphics processor.

In this paper, the FER is shown to be a possible candidate for ESD protection in deeply scaled SOI technology. I t2 of above 50 mA/µm and capacitance below 0.6 fF/µm are achieved. Despite the FER's higher resistivity than SOI diode, its major advantage is the dual-directional current shunting capability, such that ESD protection between I/O pads and power buses can be achieved with a single-device solution at the pad instead of several devices. Therefore, this device expands the conventional ESD design space for trading off parameters such as resistivity, I leak and capacitance. Results from measurements and TCAD simulations further instantiate the advantages of the FERs in current and future SOI technologies. For future technologies such as ultra-thin-film SOI and FinFET, better gate controllability can be achieved to sustain the inversion regions. Thus, the well doping can be increased to lower the resistivity, making the FER more suitable for I/O protection.