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A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 ${\mathrm{ \mu }}\text{s}$ and 500 ${\mathrm{ \mu }}\text{s}$ with the median around 10 ${\mathrm{ \mu }}\text{s}$ at room temperature.

The coefficient of variation (CV) is effective in monitoring the normalized measure of dispersion. It is extensively applied in the situations where the mean and standard deviation are not constant for all time. In this paper, the double sampling control chart is proposed to monitor the CV (abbreviated as DS-$\gamma$). Two optimization algorithms of the DS-$\gamma$ chart are developed, i.e., to minimize (i) the average number of observations to signal (ANOS) when the shift size to be known a priori and (ii) the expected average number of observations to signal (EANOS) when the shift size is unknown. The proposed chart’s performance is then compared with the standard CV chart. The results show the proposed DS- $r$ chart significantly outperforms the standard CV chart in the detection of all ranges of shifts in the CV.

The Shewhart X control chart is a useful process monitoring tool in manufacturing industries to detect the presence of assignable causes. However, it is insensitive in detecting small process shifts. To circumvent this problem, adaptive control charts are suggested. An adaptive chart enables at least one of the chart's parameters to be adjusted to increase the chart's sensitivity. Two common adaptive charts that exist in the literature are the double sampling (DS) X and variable sampling interval (VSI) X charts. This paper compares the performances of the DS X and VSI X charts, based on the average time to signal (ATS) criterion. The ATS profiles of the DS X and VSI X charts are obtained using the Mathematica and Statistical Analysis System (SAS) programs, respectively. The results show that the VSI X chart is generally superior to the DS X chart.

A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.32LSB and 0.42LSB respectively, while SNDR is 56.7 dB and SFDR is 67.8 dB at an input frequency of 400 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 3.6 mW in TSMC 0.18 m CMOS 1P6M process.

A first order error feedback based noise shaping in a double sampled ADC is proposed. This topology is ideal for nanometer CMOS technology, as it obviates the need for high-gain and high output-swing op amps and fast-settling, power-hungry, and noisy reference buffers. Using a one stage op amp with a gain of 70 (i.e. 37 dB) and output swing of ±75 mV , this topology, realized in GPDK 90-nm CMOS technology, achieves an SNDR of 60 dB operating at 1 GHz (effective sample rate of 2 GHz due to double sampling) with an OSR of 32.

The double sampling (DS) X chart is superior to the traditional Shewhart X chart in detecting small and moderate process mean shifts. In general, the DS X chart is typically designed under the assumption of known parameters. Nevertheless, the actual process parameters are rarely known in practice and are usually estimated from an in-control reference Phase I sample. In this paper, we discuss the effects of parameter estimation on the performance of the DS X chart, for both the in-control and out-of-control situations. It is found that the in-control and out-of-control performances are significantly different from the case when parameters are known, especially when the shifts and the sample sizes are small. In light of these unfavorable performances, the Phase-I sample-size recommendations are provided for practitioners in designing the DS X chart with estimated parameters, so that satisfactory performances as the case with known parameters are attained.

A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18μm CMOS process technology. The simulation results show that the SFDR of the proposed full differential double sampling circuit is 81.36dB at 200MS/s. Further simulations show that the proposed full differential double sampling circuit has twice better performance than the traditional one.

This paper describes boundary conditions for phase current reconstruction of a three current-shunt inverter and suggests a voltage injection method to expand the measurable areas. The boundary conditions are derived on voltage vector plane for symmetric space vector PWM. For the expansion of the areas, different voltages are injected depending on the position of the voltage vector with double sampling. When voltage vector is located in the insensible area, additional voltage is injected to place the voltage vector in the measurable area during next half of switching period and compensation voltage is added in the other half period. Voltages with minimum magnitudes are chosen to minimize the current ripples. Simulation results are presented to support the effectiveness of boundary condition derivation and proposed voltage injection method.

Double sampling X control chart (DS) which is a Shewhart-type chart can reduce sample size and detect small process shift fast. In real industries, process observations may be interdependent and correlated, and the statistical performance of DS X chart for the correlated data need to be re-evaluated. This article constructs the calculations of statistical indices of DS X charts for correlation data and performs a comparative study for investigating the performance distinction of DS X charts and other Shewhart-type charts. This comparative study indicates that DS X charts are the best choice for monitoring of correlated data.

In this paper, time interleaving is combined with double sampling to extend the effective sampling frequency in switched-capacitor delta sigma modulators. A Second-order four-branches delta sigma modulator is first presented. The switched-capacitor circuit is then constructed using double sampling. Results show that the effective OSR is enhanced by a factor of 8 at the expense of larger area.

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not introduce a detrimental extra factor into the loop gain. It allows the use of efficient design methods for DeltaSigma ADCs.

We developed a 10.7-MHz intermediate frequency (IF) bandpass discrete-time (DT) 4th -order 4-bit ΔΣ modulator for AM/FM car radio tuners. Using direct feed-forward and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3-kHz AM bandwidth (BW) and a DR of 94 dB in the 200-kHz FM BW. The modulator occupies 3 mm2, in 0.15 μm CMOS technology, and draws 63 mA of current.

Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon (Das et al., 2006), (Kim et al., 2005), (Worm et al., 2005), So far, reliable operation of existing link checkers - double sampling flip-flops or code-based - is not ensured over the whole range of bit error rate. Therefore, bit error rates where the checker reliability is poor are avoided either by worst-case characterisation of the link error rate (such as for double sampling flip-flops), or by constraining the operating point controller to avoid such regions (such as for code-based checkers). This paper proposes a novel checker architecture that bridges the gap between low overhead and high robustness over the whole error rate range. Specifically, the paper shows how to combine optimally double sampling flip-flops with a code-based checker (in point of reliability). The resulting checker enables simple, efficient, and reliability-agnostic operating point control policies

This paper presents a novel high-order bandpass semi-MASH sigma-delta modulator (4-2+2-...-2+2mb) with f/sub s//4 center frequency. The proposed topology employs a semi-MASH technique with a 4-2/sup L/mb topology to achieve an expandable and extendable high-order bandpass noise-shaping. To illustrate the architecture's behavior an 8xOSR 12-order 1.5-bit semi-MASH sigma-delta modulator is designed achieving 88 dB SNQR (signal-to-quantization-error ratio) at -1dB overloading point (90% of the modulator full-scale). A double-sampling mismatch-free single-opamp double-delay resonator is also proposed for the semi-MASH sub-stages to improve the overall design performance.

A dual phase switched capacitor common mode feedback (SC CMFB) circuit is proposed which is suitable for double sampling circuits. A 4/sup th/ order SC bandpass sigma delta modulator designed in CMOS is used as a testbench to compare the proposed circuit to conventional SC CMFB. The proposed circuit achieves 33 dB better image rejection and enhances the SNDR over 200 kHz bandwidth compared to the same circuit then simulated with conventional single phase switched capacitor common mode feedback.

A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process. This sensor implements digital double sampling with analog CDS on a column parallel ADC. Random noise is 5.2e-rms and the DR is 68dB at 180frames/s(6.0Gb/s). FPN is

A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandwidth while consuming 1.2mW from a 1.2V supply.

The conventional scheme for sampled-data analog decimation with rational conversion ratio of L/M(M>L) suffers from undesired distortion due to the input sample-and-hold filtering effect in the front interpolation stage. Two new impulse sampled SC FIR rational decimator architectures are proposed in this paper employing the efficient intermittent polyphase structures with Double-Sampled Active-Delayed Blocks (ADBs) which not only render them immune to the above distortion effect but also allow a significant relaxation of the amplifiers settling.

The requirements of ground vegetation data used in calibrating remotely s ensed data and checking the accuracy of the final products of remotely sensed data in vegetation studies are considered. Methods of collecting vegetation samples via a double sampling procedure which involves the t raining of observers in visual estimation and the calibration of their results are reviewed. The use of reference photographs as an aid in the visual estimation of grassland biomass is tested in the field. This method enables a rapid collection of a large number of samples to be made providing accurate ground data for use in remote sensing studies. The biomass estimates obtained via t he double sampling technique were found to be significantly correlated with biomass estimates from clipped samples at the 99% confidence level.

This paper presents a double-sampling switched-current integrator which is used to implement a second-order sigma-delta modulator. The effects of the non-ideal behavior of switched-current circuits can be summarized in a signal-dependent and independent error. Leaky integrators are the result of the signal-dependent error. It is shown that the double-sampling integrator can reduce the leak factor to the half.

This paper presents SIMULINKr modeling of the non-idealities of a bandpass sigma-delta modulator which are appropriate for behavioral simulation. Such non-idealities include clock random jitter, periodic timing-skew, op-amp non-idealities parameters (DC gain, slew-rate, gain-bandwidth, saturation voltage, capacitor mismatch and noise), and also the complete modulator noise analysis. Such modeling will be based on a real design example of a 4th-order switched-capacitor (SC) bandpass sigma-delta modulator with double sampling. Follow the top-down design manner, the behavioral simulation targets the necessary design specifications for various building blocks.

The performance of double-sampling sigma-delta A/Ds can suffer due to capacitor mismatch as well as uneven clock phases. Improving the resulting SNR is essential. This paper presents a method that uses DSP techniques to filter out the mismatch. Simulation results of applying an adaptive LMS filter to a fourth-order double-sampling bandpass sigma delta modulator are presented that show an improvement in SNR of more than 30 dB.

This 8b pipelined analog-to-digital converter (ADC) incorporates double sampling into the residue signal path of a 1.5b-per-stage architecture to effectively double the throughput of the ADC for a given analog power consumption. Residue amplifiers and sub-ADC comparators are shared between two time-interleaved channels and the sampling capacitors in the second stage are scaled in order to reduce power consumption. The ADC presented here achieves 75 MSamples/s while consuming 70 mW. The converter measures 5.5 mm/sup 2/ and is fabricated in a 3.3 V 0.5 /spl mu/m digital CMOS process with four levels of metal and no special mask layers for passive components.

A cascaded multi-bit /spl Sigma//spl Delta/ modulator uses double sampling to achieve a conversion rate of at least 4 MSample/s at an oversampling ratio of 16. Partitioned data-weighted averaging extends the dynamic range to 95 dB. The circuit, integrated in 0.5 /spl mu/m CMOS, dissipates 150 mW from a 2.5 V supply.

A new method for detection of aliasing and for reconstruction of aliased periodic signals has been developed. The basic system consists of two ADCs working at slightly different sample-rates. Therefore aliased spectral components are also shifted to each other. For certain ratios of the sample-rates the original frequency and phase of an aliased component can easily be derived. It is shown that the reconstruction is unequivocal up to half of the least common multiple of the two sample-rates