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Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. Liquid He cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES’ digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (∼1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring to minimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz. [ABSTRACT FROM PUBLISHER]

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/cm2 four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/cm2 process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1–2 μs to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated. [ABSTRACT FROM PUBLISHER]

Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics. [ABSTRACT FROM PUBLISHER]

Interfacing superconducting rapid single flux quantum logic with room temperature electronics requires the development of low-power semiconductor circuitry capable of operating at tens of Gb/s while maintaining sufficient signal to noise to achieve acceptable bit-error-rates. Such data-links must operate with sufficiently low power consumption to permit tens to hundreds of parallel channels to coexist in a single cryostat. This requires a careful trade-off between the power and noise performance of the cryogenically cooled digital amplifiers. Previously demonstrated ultra low-power cryogenic-to-room temperature digital data links have been limited to data rates on the order of a few Gb/s. In this paper we demonstrate a temperature distributed amplifier chain optimized for 30 Gb/s data transmission and consuming just 140 microwatts at 4 K. [ABSTRACT FROM PUBLISHER]

A software radio receiver that can be programmed to operate in multiple wide frequency bands is required for many communication and intelligence applications. We have designed a variety of multi-band receivers, comprising a set of band-specific analog-to-digital converters (ADCs) for direct digitization of RF bands and a digital switch matrix for band selection, in two flavors: as a single superconductor integrated circuit chip and also as a multi-chip module. In addition to the ADCs and the switch, these include a 1:16 deserializer and output drivers to facilitate transport of the digitized RF data to room temperature electronics for further processing and analysis. In the single IC flavor, up to four bandpass delta-sigma ADCs minimizing quantization noise in their respective bands were integrated on the same chip and operated at clock rates up to 20 GHz. In the multi-chip module (MCM) implementation, a 1-cm \times 1-cm universal active carrier was designed to accommodate any two 2.5-mm \times 2.5-mm flipped chips, each containing a single ADC front-end. This standardized approach facilitates customization of two-band ADCs by selecting from a growing library of ADC front-ends, which currently cover bands ranging from HF (0–30 MHz) to Ka-band (20–21 GHz). These Multi-band MCMs and single chip ADC's were fabricated, assembled and tested. [ABSTRACT FROM AUTHOR]

Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10\times 10\ mm^2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5\times 5\ mm^2 1.1-GHz bandpass ADC chip to perform world's first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5\times 5\ mm^2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm^2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application. [ABSTRACT FROM AUTHOR]

We report the development of a nano-engineered cryogenic adhesive (nECA) consisting of an epoxy impregnated with single walled carbon nanotubes (SWNT) for bonding niobium-based superconductor multi-chip modules (MCMs). The nECA offers 300%–900% enhancement in thermal conduction over the base adhesive while maintaining high electrical resistivity. Additionally, we report the thermal modeling results for a niobium-based superconducting single chip module with the incorporation of pure epoxy and nECA. When the heat flow is exclusively through the In/Sn bumps the thermal model predicts > 100 mK temperature difference between the flipped chip with active circuitry and the passive carrier substrate, which might degrade the chip's performance and the operating margins. With the use of 0.1 wt% SWNT loaded epoxy as the underfill, we report reduction of temperature differences to a more acceptable level of \sim19 mK. These results are expanded to foreseeable MCM package designs to highlight the merit of nECA as an underfill material for superconducting electronic packages. [ABSTRACT FROM AUTHOR]

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power, extended stable operation of the counter at T = 4.5 K was demonstrated with a clock frequency up to 46 GHz, with 25 mW of excess cooling capacity on the coldest stage. The thermodynamic, electromagnetic, and mechanical performance are promising for the development of an improved compact cryocooler for practical superconducting electronic applications in fields such as wireless communications. [ABSTRACT FROM AUTHOR]

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor All-Digital Receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed. [ABSTRACT FROM AUTHOR]

We report experimental results for chip-to-chip data communications on a superconducting Multi-Chip-Module (MCM) using a novel fabrication technique. The MCM was produced using a non-conductive adhesive to bond a 5-mm x 5-mm test chip to a 1-cm x 1-cm carrier. To our knowledge, this is the first time this technique was used for MCM assembly at cryogenic temperatures. The module demonstrated superior mechanical stability and protection from its environment during thermal cycling. The MCM also retained its electrical properties after multiple thermal cycling from room temperature to 4 K. We designed test circuits including various digital test benches, as well as analog test structures for bump characteristics. The superconducting circuitry successfully passed single-flux quanta at rates exceeding 50 Gbps. We measured error rates lower than 5 x 10-14 at 36Gbps using 100-micrometer-diameter In-Sn solder bumps, and lower than 6 x 10-14 at 57Gbps using 30-micrometer-diameter solder bumps. [ABSTRACT FROM AUTHOR]