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In the actual environment, the various deformations of the positioning holes of the mechanical parts and the different backgrounds will cause the circle to have irregular boundaries, which will cause the identification and positioning of the center of the circle to be inaccurate. Therefore, this paper proposes a centroid compensation algorithm based on the centroid of a circular hole. The algorithm first performs image preprocessing on the circular hole to enhance its contrast, and then performs binary and filtering processing to find its centroid. According to the binary image in the pixel The area occupied by the plane is used to identify, determine and compensate the center position of the circular hole. Experiments show that the algorithm can accurately locate the center of irregular holes with deformation, and has high accuracy and stability.

The core of driving force control strategy is the research core of electric vehicle driven by wheel motor. In order to give full play to the advantages of wheel motor drive system, a reasonable control strategy must be designed. In this paper, the stability of the vehicle is determined based on the sideslip angle of the center of mass of the vehicle. Through the speed and steering wheel angle, the actual yaw rate of the vehicle at a certain speed and the theoretical yaw rate at this speed are determined as the control objectives. The PID control is used to distribute the four-wheel brake pressure, generate additional yaw moment to adjust the vehicle attitude; and the traditional PID control is used to control the vehicle attitude. In contrast, fuzzy control using human expert control experience, for the control of nonlinear and complex objects shows the advantages of good robustness and high control performance. Therefore, on the basis of PID, through neural network learning, fuzzy neural network is used to optimize the output fuzzy rules and membership function to control the vehicle. The whole process is carried out with CarSim and Simulink Simulation is carried out to verify the control optimization process.

Rapid identification of plant disease is essential for food security. Deep learning, the latest breakthrough in computer vision, is promising for plant disease severity classification, as the method avoids the labor-intensive feature engineering and threshold-based segmentation. Using a public dataset of 54,306 images of diseased and healthy plant leaves collected under controlled conditions, a deep convolutional neural network and unsupervised methods are used to identify 14 crop species and 26 diseases. The trained model achieves an accuracy of 89.83% on a held-out test set, demonstrating the feasibility of this approach.

Socket buffer (SKB) is the standard data structure for exchanging packets and their control information between NIC driver and protocol stack. The overhead of dynamic SKB management has been considered as the significant bottleneck in packet I/O. Some novel non-SKB mechanisms, such as DPDK, were thus proposed to solve the problem. However, these mechanisms usually cannot be widely adopted in the data path of most packet forwarding applications, due to their incompatibility with SKB. In this paper, a new SKB-compatible mechanism, namely Self-described buffer (SDB), is proposed to improve the efficiency of packet I/O. SDB eliminates SKB allocation/deallocation overhead by offloading SKB management into NIC hardware. It also reduces the overhead of dynamic binding/unbinding operations existed in SKB management by statically binding related information in advance using the free space of Databuf. To evaluate the proposed approach, a SDB-enabled NIC and its driver has been designed and implemented based on FPGA. Experimental results show that the proposed SDB achieves 2× throughput compared with a traditional SKB mechanism in raw packet forwarding, and 34.75% improvement for typical network forwarding applications (e.g. IP forwarding, Bridge forwarding and SDN forwarding) on average.

In this paper, the jitter sensitivity of a real-time embedded implementation of a self-tuning generalized predictive control algorithm will be experimentally investigated using a hardware-in-the-loop testing technique. The aim of the study was to explore the potential impacts of slew rate limits of the input of the controlled system on the performance of the controller when jitter is present. The paper also examines the effects of different preemption levels of the underlying earliest deadline first scheduler on the performance of the control system.

It has been widely accepted that real-time implementations of feedback control systems can be susceptible to timing jitters which may be caused by the underlying real-time and/or embedded implementation architecture. Previous experimental studies aimed at quantifying the levels of degradation that may be observed have mainly concentrated upon relatively simple fixed-gain feedback control schemes (e.g. PID) and time-invariant plant. Although some degradation has been observed, most systems have been shown to be surprisingly robust unless driven to extreme limits. In this paper, we study the jitter sensitivity of a real-time embedded implementation of a digital parameter-adaptive control system. The purpose of the study was two-fold; primarily, to obtain empirical data related to jitter sensitivity (as measured by a quadratic performance metric), and secondarily to explore the potential impact of the underlying scheduler choice on system behavior. The findings indicate that the adaptive controller was heavily influenced by sampling jitter, and that the choice of task scheduler had a role to play.

It is well known that the performance of real-time control applications can be seriously degraded by sampling and actuation jitters and delays. This paper describes a simple hybrid-EDF algorithm which may help to ameliorate some of these problems in resource-constrained embedded systems in which the use of simplified and non-preemptive schedulers is required. The algorithm supports a single preemptive time-critical sampling and actuation task, whilst the remaining tasks are executed non-preemptively and have implicit deadlines. The paper develops an efficient schedulability analysis technique for this framework; analysis and an example are given to illustrate the improvement in efficiency over related techniques.

It is well known that the performance of real-time control applications can be affected by many factors, including the choice (and configuration) of the hardware platform and task scheduling algorithm. This paper presents a real-time hardware-in-the-loop simulation tool that simultaneously integrates concepts from control and real-time computing to allow further investigation into these links. It allows the experimental prototyping and analysis of real-time control systems on real hardware — but within a simulated plant environment -and thus allows the potential impacts of hardware and software architecture on control performance and dependability to be evaluated. The structure of the proposed tool is described, along with a preliminary experiment that has been performed to illustrate some of the test facility capabilities.

Requirements are strict in Streaming media technology for network bandwidth, audio/video real-time data transmission and continuous playback. At the same time, the user also has a certain requirements in quality of service of streaming media application QoS(Quality of Service), and asks the system to provide a commitment for network bandwidth, end to end delay, physical jitter, packet error rate and other index. Therefore, how to build strong QoS management mechanisms to meet the requirements of users is imminent. However, its monitoring technology has no uniform standard to support. There are some limitations in the current indicators, so this paper proposes packet transmission time based on monitoring indicators calculated index of VTD (Video Timestamp Dithering), which is not only widely applied, but also timelier and accurate reflection of the network jitter.

This paper describes a hybrid object-based video coding scheme that achieves efficient compression by separating moving objects from stationary background and transmitting the shape, motion and residuals for each segmented object. In this scheme, a new content-based object segmentation algorithm is proposed, which does not assume any prior modeling of the objects being segmented. The binarization process, which finds large object regions, is based on a threshold function that calculates block histograms and takes image noise into account. The resultant binary mask is further processed using morphological operations. The motion vectors are estimated inside the change detection mask using block-matching method between two successive frames, and then the dense motion field is estimated using the motion vectors and the Horn-Schunck algorithm.

This paper presents a new video segmentation scheme, which consists of two stages: initial segmentation and motion estimation. In the initial segmentation, the watershed transformation followed by a region adjacency graph guided region merging process is used to partition the first video frame into spatial homogenous regions. Then the motion of changed region is estimated. Based on the highly efficient quadratic motion model, the motion estimation is undertaken using Gauss-Newton Levenberg-Marquardt method to minimize the least-square error function. Experimental results show the proposed scheme provides high performance in terms of segmentation accuracy and video compression ratio.

Video sequences often suffer from jerky movements between successive frames. In this paper we present a stabilisation method to extract the information from successive frames and to correct the undesirable effects. In the method, the optical flow is computed and the estimated motion vectors using the Horn-Schunck algorithm are passed to the model-fitting unit that stabilizes and smoothens the video sequence. A synchronization module supervises the whole system. The measures based on the fidelity of the system (PSNR) are given to demonstrate the stabilisation and efficiency of the system.

This paper presents an improved driver circuit design for boost DC-DC converter applications. The circuit possesses the characteristics of low power supply and high speed and is, thus, suitable for portable equipment and mobile applications. The simulation results demonstrate that the design has achieved a low power voltage of 1.0 V, which is ideal for single battery applications. The operational frequency of the circuit can be as high as 1 MHz, which meets the increasing demand for high switch speed. Using Samsung bipolar process, this design has been prototyped, and the testing on chips confirms that the prototypes fully meet design specifications and are ready for commercial products applications.

This paper presents a CMOS band-gap reference design, which possesses the characteristics of low noise and high power supply rejection capability. Thus, it is suitable for the applications of a wide range of frequency and power input. In order to reduce thermal noise and to provide the output reference voltage that is resistant to power supply variations, the design incorporates an RC filter into conventional reference structure. Moreover, a fast turn-on circuit is introduced into the design to improve turn-on time of the circuit. The simulation results show that within the frequency range from 100 Hz to 10 MHz, the design has achieved an average power supply rejection ratio (PSRR) of more than 80 dB and an average noise of 8.5 /spl mu/Vrms. With the fast turn-on circuit, the improved band-gap reference circuit can reach its steady state within 100 microseconds.

A cascaded H-bridge multilevel inverter based active power filter with a novel direct power control is proposed in this paper. It can be directly connected to medium/high voltage power line without using the bulky transformer or passive filter. Due to the limited switching frequency (typically below 1 kHz) of high-power solid-state devices (GTO/IGCT), multiple synchronous/stationary reference frame current controllers are reviewed and derived. Based on this, a novel current controller is proposed for harmonic current elimination and system power factor compensation. Furthermore, a synchronous/stationary hybrid structure can be derived with fundamental de-coupling control. The instantaneous reactive power theory and synchronous reference frame based control are compared based on mathematical models. A direct power control concept is then derived and proposed. It is equivalent as the hybrid synchronous/stationary frame current controller, but has a simpler implementation. It has clear physical meaning and can be considered as a simplified version of the hybrid frame current controller. Simulations on a 4160 V/1.2 MVA system and experimental results on a 208 V/6 kVA laboratory prototype are presented to validate the proposed active power filter design.

This paper presents an improved sample/hold (S/H) circuit design for analog LCD applications. The circuit possesses the dual characteristics of high sampling precision and low switch noise and is thus suitable for video signal sampling applications. In order to increase accuracy of sampling and to reduce switch noise, the design uses an operational amplifier with current-mode switch, which incorporates an improved buffer amplifier, and introduces a noise elimination technique by using a differential amplifier. The simulation results show that for a typical signal sampling application and its BiCMOS implementation, the design has achieved a minimal signal distortion and significantly reduced noise effect.

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.

An improved three-step search (ITSS) block-matching algorithm for motion estimation is described, specifically aiming towards low bit-rate video-coding applications. The method is based on the real-world image sequence's characteristic of centre-biased motion vector distribution, and uses centre-biased checking point patterns and a relatively small number of search locations to perform fast block matching. The computational complexity is reduced by employing an 11/spl times/11 search window rather than the traditional 15/spl times/15 window. Simulation results are presented which show that the ITSS algorithm provides better performance at a faster speed than the well-known three-step search (TSS) algorithm and the previously developed new three-step search (NTSS) algorithm when used for low bit-rate video coding, such as in the video telephone and video conferencing.

In this paper, we proposed a flexible VLSI-based parallel processing architecture for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

This paper presents a low-cost frame grabber, which was specifically designed as part of a real-time motion detection system for high-resolution images. The frame grabber is FPGA-based to minimise size of the PCB and improve reliability of the system. It also acts as a backend add-on card for an IBM-PC compatible. The experimental tests carried out on different machines show that the board implemented meets all specifications required by the system, and performs well. The captured frames are clear, well contrasted and jitter-free in both live and still video modes and their quality is comparable to that available from equivalent commercial systems.