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In this work, the RF performance comparison of lateral and vertical tunnel FETs is presented in the context of ultra low power (ULP) Internet-of-Things (IoT) sensor node circuit applications. It is demonstrated that at low drive currents $(\sim 1\mu \mathrm{A/\mu m})$ , LTFETs outperform VTFETs by an order higher cut-off frequency $(f_{\mathrm{T}})$ of 10 GHz, maximum oscillation frequency $(f_{\mathrm{MAX}})$ of 100 GHz and 50% higher intrinsic gain (Avo). The results show that the TFETs are promising as ULP devices $(V_{\mathrm{ds}}=0.5$ V or less).

A comparative analysis of ULP analog/RF performance metrics have been presented. TFETs will be useful in high-gain ULP circuits with limited bandwidth requirement. Underlap INV and JL devices, achieving a balance between gain and bandwidth, are most suitable for ULP analog/RF applications. JL MOSFETs do not suffer from any significant degradation in metrics despite higher channel doping.

In this work, we report on the doping dependence of RF performance metrics of junctionless transistors and compare the same with conventional undoped inversion mode MOSFETs. It is demonstrated that at low drive currents (~ 25 μA/μm), JL transistors outperform inversion mode MOSFETs as 20% to 40% higher values of cut-off frequency is obtained for all doping concentrations (1019 cm3 to 3×1019 cm3). It is shown that the junctionless device architecture is advantageous for ultra low power RF applications as parasitic capacitances are significantly reduced. Scaling trends for cut-off frequency (at lower drain currents) with respect to gate length highlights the potential of junctionless architecture for ultra low power applications.

This work reports on possible ways of improving analog/RF performance metrics, through device structure optimization, for low power applications. It is shown that underlap source/drain (S/D) design and junctionless transistor architecture can both yield improved analog/RF figures of merit in comparison to conventional abrupt source/drain MOSFETs. Junctionless devices overcome the gain-bandwidth trade-off associated with analog design. The results are significant for RFICs in emerging ultra-low-power technologies.

In this work, we analyze the dependence of steep subthreshold (S-slope) on device and bias parameters of Junctionless (JL) MOSFETs. It is observed that for certain parameters and bias conditions, the JL transistor cannot be turned OFF resulting in a single transistor latch. This phenomenon is an extreme case of impact ionization in JL MOSFETs. It is shown that thicker values of silicon film thickness and gate oxide along with higher drain bias can drive the JL MOSFET in to the latch state.

The present work reports on the substantial benefits of underlap Source/Drain (S/D) design in moderately inverted nanoscale MOSFETs to significantly enhance key analog/RF performance metrics. It is demonstrated that underlap S/D design alleviates the inherent trade-offs between bandwidth, gain and linearity for low power RF CMOS nanodevices. Optimal underlap region parameters are identified and design trade-offs examined. The results are significant for RFICs with nanoscale MOSFETs in emerging technologies.

In this work, we analyze the sensitivity of steep subthreshold slope (S-slope) values exhibited by Junctionless (JL) MOSFETs on device parameters. The steep S-slope values (< 60 mV/decade) achieved by JL MOSFET due to impact ionization are more sensitive to film thickness than gate length and oxide thickness. JL MOSFETs designed with higher doping concentrations show steeper S-slope values at lower drain bias than those doped with lower doping concentrations. It is demonstrated that for certain set of parameters, steep S-slope JL nanotransistors can latch to the on state and fail to turn-off. The work identifies the possible set of device parameters for which steep S-slope values can be observed in JL nanotransistors.

The evolution of self-similar parabolic pulses is demonstrated by designing a parabolic index dispersion decreasing fiber amplifier with normal dispersion (ND-DDF amplifier), with inclusion of the variation of nonlinear factor (gamma) with distance. The pulse transmission is extensively studied for the proposed ND-DDF in presence of external gain as well as virtual gain induced by its dispersion profile. The output power resembles with a perfect parabolic shape giving rise to self-similar pulses with minimum misfit les 0.003. In view of practical aspects of fabrication we also obtain several equivalent staircase profiles, whose performances are shown to be very close to that of the proposed ND-DDF.

A 1.6 GHz power oscillator with a GaN-on-Si heterostructure field effect transistor (HFET) is reported. The voltage-controlled oscillator used a thin-film barium strontium titanate (BST) interdigital varactor as the tuning element. The surface-mount varactor was fabricated using sputtered BST film and copper metallization on alumina. An output power of 1.6 W (32 dBm) is obtained with a DC conversion efficiency of 25.5%. Flat tuning sensitivity of 500 kHz/V, 49 MHz linear frequency tuning, and power flatness of better than 0.5 dB are obtained with 0?100 V tuning voltage. The maximum oscillator phase noise is ?81.4 dBc/Hz at 100 kHz offset..

Barium strontium titanate (BST) has a field-dependent permittivity and can be used as a dielectric in voltage tunable capacitors or varactors. These BST-based varactors are passive devices and have significantly different properties compared to semiconductor varactors. A voltage tunable oscillator using a BST thin film varactor was designed and characterized. The frequency of oscillation varied from 34.8 MHz to 44.5 MHz (28% tuning) upon application of 7 V tuning voltage. The VCO gain was 1.38 MHz/V and the 2nd harmonic was over 23 dB below the fundamental throughout the tuning range.