Search

An improved EEHEMT nonlinear model with noise model has been developed in this paper. Empirical formulas of bias dependent noise model parameters are given. A four-stage 120–160 GHz monolithic low-noise amplifier (LNA) fabricated with the 70nm InAlAs/InGaAs/InP HEMT technology. The simulated results of S-parameters and noise figure show the good agreement with measured data to verify the accuracy of the proposed model.

The study focuses on analysing the high-level carrier lifetime ( $\tau _{\mathrm {HL}}$ ) in 4H silicon carbide (4H-SiC) PiN diodes under varying temperatures and proton implantation doses. The objective is to identify an empirical law applicable in technology computer-aided design (TCAD) modelling for SiC devices, describing the dependence of carrier lifetime on temperature to gain insights into how irradiation dose may influence the $\tau _{\mathrm {HL}}$ . We electrically characterize diodes of different diameters subjected to different proton irradiation doses and examine the variations in current-voltage (I-V) and ideality factor (n) curves under various irradiation conditions. The effects of proton irradiation on the epitaxial layer are analysed through capacitance-voltage (C-V) measurements. We correlate the observed effects on I-V, n, and C-V curves to the hypothesis of formation of acceptor-type defects related to carbon vacancies, specifically the Z $_{\mathrm {1/2}}$ defects generated during the irradiation process. The impact of irradiation on carrier lifetime is investigated by measuring $\tau _{\mathrm {HL}}$ using the open circuit voltage decay (OCVD) technique at different temperatures on diodes exposed to various H+ irradiation doses with constant ion energy. This investigation reveals the presence of a proportional relationship between 1/ $\tau _{\mathrm {HL}}$ and the dose of irradiated protons: the proportionality coefficient, referred to as the damage coefficient (K $_{\mathrm {T}}$ ), exhibits an Arrhenius-type dependence on temperature. OCVD-measured lifetime on the various diodes demonstrates a power-law dependence of lifetime on temperature. The exponent of this dependence varies with the irradiation dose, notably showing an increase in temperature dependence at the highest H+ ion dose. This suggests a threshold-like dependence on H+ irradiation dose in the $\tau _{\mathrm {HL}}$ -temperature relationship.

Capacitance-voltage (C-V) measurements play a crucial role in evaluating semiconductor device performance by revealing vital parameters such as doping levels and charge carrier behavior. This study specifically investigates the impact of mesa structures on C-V measurements in 4H-SiC PiN vertical diodes. Our analysis uncovers distinct capacitance values per unit area among diodes with varying diameters within the same diode family. These findings underscore the limitations of conventional capacitance equations formulated for planar devices when extended to mesa-structured devices. To separate the capacitance portion dependent solely on the PN junction’s area from the overall depletion capacitance, which is influenced by the device’s geometry, we applied a methodology involving multiple C-V measurements across diodes with differing diameters and validated the experimental outcomes through rigorous calculations. This enables the utilization of standard capacitance equations. Neglecting the impact of device geometry has the potential to introduce significant inaccuracies in critical device parameters. The proposed methodology addresses these limitations, offering valuable insights to enhance the accuracy of extracted quantities from C-V measurements. Furthermore, it provides guidance for interpreting experimental data obtained from devices incorporating mesa structures.

Comprehensive analysis of small-signal equivalent circuit models for GaAs-based PIN diodes is performed in this article. The analysis provides the equivalent circuit models for PIN diode operation in four different operation modes. A compact nonlinear equivalent circuit model has been developed which takes into account the dc/ac frequency dispersion of the diode dynamic resistance. In order to verify the validity of the proposed circuit model, the comparison between the modeled and measurement data is given, good fitting is obtained for GaAs-based PIN diode. [ABSTRACT FROM AUTHOR]

In this article, a complete and efficient wireless power transfer (WPT) system, consisting of a full-duplex antenna, a half-wave rectifier, and a WPT transmitter (Tx), is designed and validated for deep-body ingestible biomedical capsules. A two-port full-duplex antenna is adopted to perform seamless telemetry and to act as a receiver for WPT Tx without using a multiplexer circuit. The full-duplex implantable antenna operates at 915 MHz (Port 1) and 1300 MHz (Port 2) and occupies compact dimensions of 8 $\times $ 8 $\times $ 0.13 mm 3. It maintains high isolation of >30 dB and peak realized gains of −19.3 dBi at 915 MHz and −17.7 dBi at 1300 MHz. The miniaturization of this antenna is achieved using semicircular slots on the patch and circular slots on the ground plane while mutual coupling between the ports is reduced by a series of metallic vias. Moreover, a low-profile and efficient rectifier is designed at 1300 MHz and integrated with port 2 of the antenna. The suggested rectifier achieves a radio frequency (RF) to direct current (dc) conversion efficiency of 80.4% at an input power of 1 dBm. Furthermore, a patterned patch antenna is designed that acts as a WPT Tx for the biomedical capsule. After examining the individual performance of the antenna, rectifier, and WPT Tx, the overall WPT system is then validated by placing the capsule (rectifier integrated antenna) inside minced pork meat and powered by the WPT Tx. This WPT system is suitable for modern capsule devices due to its features, such as compact size, high gains, high RF-dc conversion efficiency, simultaneous wireless powering and telemetry, and high-power transfer efficiency (PTE). [ABSTRACT FROM AUTHOR]

Semi-analytical method for the determination of extrinsic and intrinsic model parameters for GaAs-based p-i-n diode is presented in this article. The main advantage is that the air-bridge interconnect inductance is regarded as an independent element and can be distinguished from the feedline effect. The detail model parameters extraction procedure is proposed, and the corresponding closed-form expressions are derived. Good agreement is obtained between the simulated and measured S-parameters up to 110 GHz to verify the validity of the approach. [ABSTRACT FROM AUTHOR]

The helical cathode is one of the classical structures of the cathode for the microwave tube, and has a wide application in pulse transmission tube. In this article, we propose a quantitative expression of the space charge limited current (SCLC) of the helical cathode diode through improve the theoretical model of Japanese distinguished scholar Y. Koike, and study the dependence of the SCLC of the helical cathode diode with radius of the cathode filament ($r_{f}$), cathode height ($H$), helical pitch ($d$), and anode voltage ($V$), respectively. The results show that the value of current is an increasing function of $r_{f}$ , $H$ , and $V$ , and a decreasing function of $d$. The simulation results show that when the radius of the cathode filament is greater than or equal to 1.6 mm, the proposed model of this article is more suitable than Y. Koike’s model, and can be used in combination with Y. Koike’s model to estimate quantitatively the SCLC of helical cathode diode. Moreover, it also provides an effective basis for the design and optimization of the helical cathode structure of the microwave tube. [ABSTRACT FROM AUTHOR]

The circuit formed by a diode with series resistance is a basic electronic circuit whose analytical solution of the electrical current requires the usage of the Lambert ${W}$ function. However, in circuits where the current-voltage relation follows a power-law, like in an RCD (resistor-capacitor-diode) circuit in the continuous-time domain, the Lambert function is not useful. The power-law behavior also appears in some nanostructures like in the Mark-Helfrich equation for the space charge limited current in nanowires. In this work, we provide analytical solutions for both cases using the recently proposed Lambert-Tsallis ${W} _{q}$ function, showing that the ${W} _{q}$ function is a useful mathematical tool for finding analytical solutions of electronic circuit equations where the current-voltage characteristics follows a power-law. [ABSTRACT FROM AUTHOR]

This paper proposes a varactor-based circuit technique intended for amplitude and phase control, with improved linearity in the presence of parasitic capacitances and parasitic inductances. The mechanism causing linearity degradation in an anti-series varactor network that includes significant parasitic elements – a key aspect that, to our knowledge, has never been reported – is first studied using an analytical approach based on multi-tone excitation. It is demonstrated that simply optimizing the ratio of diode sizes is insufficient to circumvent this linearity degradation. The underlying linearity degradation concept serves as the basis for the introduction of a modified anti-series controllable capacitance, followed by a design and practical implementation. Experimental validations with multi-tone and modulated signals demonstrate improved linearity performances with respect to the state-of-the-art when parasitic capacitances and inductances are significant. Moreover, it is shown that the complete varactor-based circuit topology proposed here, which uses the proposed modified anti-series controllable capacitance in conjunction with a second-harmonic trap filter, constitutes a very attractive alternative to the state-of-the-art anti-series/anti-parallel topology, since it reduces the required number of diodes by a factor of 2. Measurements on discrete-component designs operating at 3.6GHz, hence with significant parasitic effects, demonstrate that the proposed circuit topology improves the 3rd order intermodulation distortion levels by 10.6dB and 6.6dB at output powers of 10dBm and 18dBm respectively, in comparison with the state-of-the-art topology. Measurements with a 16QAM modulated signal also show 3.9dB improvement in ACPR at 18dBm. These performances constitute improved state-of-the-art results in anti-series hyper-abrupt varactor-based electronic control.

A novel fixed frequency beam-steering leaky-wave antenna (LWA) is presented in this manuscript. Radiation occurs through thin offset longitudinal slots etched on a substrate integrated waveguide (SIW). The beam-steering is achieved by implementing GaAs varactor diodes on the backside of the antenna. Sweeping the bias voltage from 1V to 15V causes the phase constant variation, leading to the 25° beam-steering at 28.5 GHz. The key novelties of the proposed reconfigurable antenna are the low-profile and electronic beam-steering capability using a single varactor diode per cell located on the antenna’s backside. Moreover, placing the components on the backside reduces the unwanted blockage effects on the radiation. The antenna’s thickness, length, and width are 0.32 mm, 95 mm, 24 mm, respectively. The measured peak realized gain of the proposed antenna at 28.5 GHz is 9 ± 0.8 dBi. Low-profile, small gain variation, ease of fabrication, and electronic beam-steering capability make the proposed LWA suitable for the 5G beam-steering applications. A detailed sensitivity analysis along with the experimental validations were performed to prove the validity of the proposed novel design.

A technically easy way to reproduce lightning current pulses is to use a capacitive high-current impulse generator with a crowbar switch. For the crowbar switch, commonly spark-gaps are used which can withstand the mechanical and thermal stress due to the high current pulses. The spark-gap is triggered by an external high voltage trigger-device when the oscillating current attains the maximum. For extremely high currents, it is a common method to combine two of such generators to a tandem generator. In this case, it is necessary that the crowbar switches of both generators are triggered time-synchronized and decoupled by the use of an inductance. In order to avoid the triggering and the decoupling of the crowbar switches, we replaced the spark-gaps of both crowbar switches of our tandem generator by two diode-stacks, each consisting of 25 high-power diodes. After this modification, the tandem generator is able to reproduce even extremely high lightning currents as the 10/350 μs current pulse up to a level of more than 300 kA. The use of the diode-stacks also allows to combine the high-current generator with other current generators as a long duration current generator used for the experimental simulation of the continuing currents. Because no decoupling inductance is needed and the arc of the spark gap is avoided, the tandem generator is now able to test equipment with higher inductance and resistance compared to the generator with spark-gap based crowbar switch. [ABSTRACT FROM AUTHOR]

This work presents a ${D}$ -band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 $\mu \text{m}\,\,\times1448\,\,\mu \text{m}$. Together with the package the sensor measures a size of 42.2 mm $\times42.2$ mm $\times45.7$ mm. [ABSTRACT FROM AUTHOR]

On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical ESD protection designs, which cannot be addressed by 2D TCAD ESD simulation. This article reports a comprehensive ESD simulation analysis by comparing true 3D TCAD with 2D TCAD, using exemplar diode ESD devices in a 55nm CMOS, which reveals 3D ESD discharging behaviors upon ESD layout variations. It concludes that true 3D TCAD ESD simulation is a powerful technique to enable ESD layout design optimization in real-world ESD protection designs.

Branch-line couplers (BLCs) are commonly used in the wireless systems. To achieve reconfigurable applications, switchable BLCs with p-i-n diodes can be used. Several studies have used diode parasitic reverse-biased capacitor and forward-biased inductor to approach off and on states. Although the capacitance and inductance are usually low, the parasitic effect may degrade predicted switching responses. This study proposes five reconfigurable switching microstrip BLCs. Each of the first two presented BLCs uses shunt to ground diodes for realizing two switching modes. The first mode with reverse-biased capacitors for perfect matching design is equivalent to a conventional branch-line coupler (BLC). The second mode uses low forward-biased inductances to approach shunt to ground, which transfers most signal power from Port 1 to Port 2/4; however, parasitic inductors produce some mismatches. To improve this problem, the proposed third or fourth BLC achieves two perfect matching modes by using shunt stub-loaded diodes. Specifically, by using four stub-loaded diodes, the proposed final BLC exhibits three perfect matching modes and one perfect isolation mode under a lossless ideal circuit condition.

Simple low-temperature pulsed power dissociation method for high resistive liquid is proposed in this article. Active high voltage rebound tailing pulse (RTP) diodes are adopted to conventional high voltage pulse power sources. In order to explain this method, the study was performed using deionized water (DIW) (high resistive $>17~\text{M}\Omega \cdot $ cm) electrolysis with two immersed electrodes. The forward pulses, the full-width at half-maximum (FWHM) of 400 ns and forward voltage (7 kV) with rising-up ratio (dV/dt) of 1011 V/s, were applied to the electrodes. When a 5 kV RTP diode was simply adopted to this electrical circuit and DIW load in series, the high forward voltage pulse and continuous high reverse current were applied to this circuit. Then, H2 was generated at the anode electrode and OH radical (OH) in the water vessel. Those phenomena were apparently dependent on the anode electrode area. At the beginning of the forwarded high voltage application, the circuit behaved as capacitance load with generated ions and built up charges at the interface between DIW and the electrode. Continuous rebounded high reverse voltage and highly built-up reverse recovery charges induce avalanche breakdown of RTP diode. The rebounded electrical current was found to be collected in the circuit, accompanied by the generation of hydrogen and OH, as well as the tailing current flowing at the interface as a resistive load. In consequence, we point out that rebounded electrons injected from the surrounding water to the anode electrode interface induced the water electrolysis characteristically, according to RTP-diode inserted in the circuit. [ABSTRACT FROM AUTHOR]

Vertical biristors are small footprint (${4}{F}^{{2}}$) floating base bipolar junction transistors (BJTs) proposed for high-speed volatile memory applications. One key challenge is (i) the high latch-up voltage with Si-based biristors because of the high threshold of impact ionization (II) in Si. In this article, an epitaxial ${n}^{+}/{i}/{\delta {p}}^{+}/{i}/{n}^{+}$ -based vertical biristor is proposed with an asymmetric doping profile that enables sub-bandgap II only in the negative polarity. First, in the negative polarity, a latch-up voltage as low as 0.5 V due to sub-bandgap II is demonstrated. Faster programming with higher bias is observed. Second, erase is demonstrated in the positive bias, where II is insignificant. Overall, a large read window (${\Delta } {I}=\text {0.01 mA}$) with a low variability (${\sigma /\mu }$ in ${\Delta }{I}$) for cycle-to-cycle (C2C < 1%) and device-to-device (D2D < 5%). Retention in excess of $1 {\mu }\text{s}$ is observed, taking into account C2C and D2D variations. A high endurance (> 107cycles) is also observed. Therefore, asymmetrically doped vertical biristor is promising for very low voltage high speed memory application compared to dynamic random access memory (DRAM). [ABSTRACT FROM AUTHOR]

The CMOS silicon avalanche-mode light-emitting diode (AMLED) has emerged as a potential light source for monolithic optical interconnects. Earlier we presented a superjunction light-emitting diode (SJLED) that offers a higher electroluminescent intensity compared to a conventional AMLED because of its more uniform field distribution. However, for reducing power consumption low-voltage ($\leq 15\text{V}$) SJLEDs are desired, not explored before. In this work we present a TCAD simulation feasibility study of the low-voltage SJLED for various doping concentrations and device dimensions. The results show that for obtaining a constant field, approximately a tenfold more aggressive charge balance condition in the SJLED is estimated than traditionally reported. This is important for establishing a guideline to realize optimized RESURF and SJLEDs in the ever-shrinking advanced CMOS nodes. [ABSTRACT FROM AUTHOR]

In this article, a β-Ga2O3 metal-interlayer-semiconductor Schottky barrier diode (MIS-SBD) using Al-reacted aluminum oxide as the interlayer is demonstrated for the first time and compared with conventional metal-semiconductor (MS) Schottky barrier diode (SBD). The aluminum oxide is formed by sputtering a thin Al layer on Ga2O3 substrate and then annealed in O2 at 300 °C. With the insertion of Al-reacted interlayer, the SBD subthreshold swing (SS) is significantly improved to 61 mV/dec with an average current range of > 6 orders. Example of atomic layer deposited (ALD) Al2O3 as the interlayer is also fabricated and characterized. J – V study corrected by Gaussian distribution model shows that all the samples statistically exhibit similar mean barrier heights (BHs). This indicates that the interlayer hardly affects the electrostatic field and band bending as experienced by carrier injections. C – V study provides different BH results in different sample setups. The result proves that Al-reacted interfacial layer helps eliminate interface degradation as compared with ALD Al2O3. Overall, MIS-SBD by Al-reaction method exhibits improved SS, reduced reverse leakage current (I0), low ideality factor, good ON-OFF ratio (> 109), and minimized interface charges as compared with its respective counterparts. The result of this article serves as a promising interface engineering technique for Ga2O3-based SBD designs. [ABSTRACT FROM AUTHOR]

Ion- and terrestrial neutron-induced single-event burnout (SEB) data indicate that a thicker, more lightly doped epitaxial (epi) region significantly increases the threshold at which ion-induced SEB occurs in silicon carbide (SiC) power MOSFETs and junction barrier Schottky (JBS) diodes. Simulations indicate that the reduction of power dissipation along the core of the ion track is responsible for the increased robustness of the devices that have higher breakdown voltage ratings. Implications for circuit design show that using a 3300-V power MOSFET provides a significant increase in SEB threshold margin compared to a 1200-V MOSFET, with minor impact on power dissipation during normal operation. [ABSTRACT FROM AUTHOR]

Dopant segregation (DS) technique has been extensively employed to tune Schottky barrier heights (SBHs) of NiSi/Si diodes, either leading to reduced specific contact resistivity (ρc) in source/drain (S/D) Ohmic contacts, or enhanced current drivability in Schottky barrier S/D MOSFET (SB-MOSFET) where metallic NiSi is employed as S/D. A capacitance–voltage (C – V) method is usually adopted to reliably extract the SBHs of NiSi/Si for investigating the effectiveness of such a DS technique. In order to avoid large reverse leakage current which rules out the possibility of SBHs extraction during C – V measurements, dopants with opposite polarity to that in epitaxial Si substrate segregate at the NiSi/Si interface, for instance, boron DS (B DS) for NiSi/n-Si and arsenic DS (As DS) for NiSi/p–Si. This, however, raises one critical question, i.e., NiSi/p+–Si (B DS)/n-Si and NiSi/n+–Si (As DS)/p–Si are p–n or Schottky junctions. In this work, a dedicated circuit is devised to distinguish the type of as-fabricated NiSi/Si diodes with DS based on different switching mechanisms between p-n and Schottky junctions. [ABSTRACT FROM AUTHOR]

In this letter, a 400-nm-thick β-Ga2O3 nanomembrane is extracted from an n-Ga2O3-on-silicon wafer by wet etching, and then transferred to a p-GaN/ sapphire wafer by transfer-print technique to fabricate n-Ga2O3/p-GaN heterojunction diodes. X-ray photoelectron spectroscopy (XPS) measurement is used to accurately confirm that the valence-band offset of the heterojunction is 1.41± 0.07 eV. The diodes exhibit excellent electrical properties including high rectification ratio (3.85 × 106 at ±5 V) and low reversed current density (1.51 × 10−7 A ⋅ cm−2 at −5 V). The results show that the lift-off and transfer-print processes pave a new way for fabricating high-performance Ga2O3-based heterojunctions and bipolar devices. [ABSTRACT FROM AUTHOR]

The transient overshoot behavior of bipolar devices is investigated by means of very fast transmission line pulses (VF-TLP). All devices under investigation, a forward biased diode, an open base transistor and a SCR comprise a lowly doped region (LDR). Measurements have been done for rise times of 0.3ns and 1ns. To separate the voltage drop inside the device from parasitic contributions TCAD simulations have been performed. The analysis shows that for a fixed length of LDR the effect of the lowly doped region depends on the type of the device and is linked to the charge carrier distribution inside the LDR. In addition, the effect of the length of the LDR on transient voltage overshoot is compared for a forward biased diode and an SCR. [ABSTRACT FROM AUTHOR]

Critical design parameters for AlGaN/GaN Schottky barrier diodes (SBDs) are analyzed in this work using TCAD computations and detailed experiments. A comprehensive TCAD-based computational modeling approach is developed for GaN-based SBD. Breakdown mechanisms in SBD for unintentionally doped (UID) buffer, Fe-doped buffer and C-doped buffer are studied. For the first time, we have reported impact of anode recess, on breakdown and leakage behavior of SBD, in correlation with interface defects. Using these insights an optimum recess design strategy has been presented and is validated experimentally. Furthermore, for the first time, we have revealed critical repercussions of the field plate termination on SBD’s breakdown, leakage as well as transient behavior. Forward and reverse recovery measurements were carried out to study the diode’s transient performance as a function of field plate design. Various performance matrices such as diode current collapse, reverse current overshoot and reverse recovery time were studied experimentally as a function of field plate design. Moreover, the field plate-dependent electro-thermal behavior of SBD was studied using TCAD computations and experiments. Using the systematic device design approach we have experimentally demonstrated large periphery SBD with 15 A forward current at 5.5 V. [ABSTRACT FROM AUTHOR]

In this article, a novel structure design concept [plasma spreading layer (PSL)] is introduced into silicon carbide (SiC) merged PiN Schottky (MPS) diode to improve the surge current capability. Compared to the isolated P+ island design in traditional MPS diode, the P+ islands in the proposed new structure are connected by the P+ plasma spreading layers which can spread bipolar current from P+ islands to the other parts of the device during the surge pulse. Therefore, the effective conducting area of the device is increased and the energy dissipation capability can be improved. In this article, 1.2-kV SiC MPS diodes with two types of plasma spreading layers are designed and fabricated. Their forward characteristics and surge current capability are compared to traditional stripe cell and hexagonal cell designed MPS diodes. The experimental results show that, with the help of the plasma spreading layers, a 20% increase of energy dissipation capability is achieved by the new structure design, which results in a 10% improvement of the surge current capability. [ABSTRACT FROM AUTHOR]

Low on/off ratio gravely hinders the application of magnetoresistance (MR) devices for the accurate and reliable data fetch. In this paper, a rectified tunnel MR (R-TMR) device is fabricated by integrating perpendicular-magnetic-anisotropy magnetic tunnel junction (PMA MTJ) and Schottky diode. High on/off ratio, intrinsic non-volatility and multi-dimensional regulation capabilities can be obtained, which makes this emerging spintronic device suitable for in-memory computing (IMC). By reversing the rectifying direction of the diode and tuning the proportions of alternating current (AC) and direct current (DC), reconfigurable logic operations have been achieved. Two proofs of concept, i.e. “NOR” and “NAND”, are experimentally performed. [ABSTRACT FROM AUTHOR]

Power electronics demand appropriate heat dissipation to secure life span, reliability, and power density. Among several cooling methods, oil immersion is an efficient and cost effective one. Natural convection is the most reliable considering the lack of pumps and fans compared to other practical ways of immersion cooling. This article brings a case study of a power electronics device submerged in an oil tank, the same one used for power transformers. Using computational fluid dynamics simulations and an experimental setup, the natural convection process is demonstrated as well as the better heat flow dissipation of oil immersion cooling. [ABSTRACT FROM AUTHOR]

This article describes a full-bridge rectifier and a receiving antenna array for operation within an innovative wireless power transmission (WPT) system. A high-power transmitter using circularly polarized free-space waves and based on a retrodirective antenna array technology is also employed to boost the overall received RF power at the input of the rectenna. To the best of our knowledge, the proposed rectifier circuit and active antenna configuration are the first demonstration of a high-power beam tracking system for WPT scenarios, being different from previously reported near-field coupling and other lower power harvesting schemes. The main focus of this article is the rectifier design, its bench-top measurements, and operation in such a retrodirective, self-tracking microwave system. A novel approach based on in-phase multitone input signals is also developed to improve rectifier efficiency. The rectifier size is 4.5 cm by 2 cm and can offer more than 86% and 75% RF-to-dc rectification efficiency at 27 dBm for an input signal at 1.7 and 2.4 GHz, respectively. This rectifier circuit component can also be employed in other communication applications or WPT systems, for example, to convert to dc received RF signals or power in the radiating near- and far-field in order to wirelessly charge the batteries of home electronics, such as smartphones, tablets, or Internet of Things (IoT) devices. [ABSTRACT FROM AUTHOR]

Layered van der Waals (vdW) semiconductors have emerged as preferred materials for building next-generation electronic devices, such as diodes and field-effect transistors (FETs), because of their capability of providing high mobility at the nanometer-scale thickness, as well as their flexibility and pristine interfaces. However, the inherent “vdW gaps” in these materials lead to much larger cross-plane resistivity, with respect to in-plane resistivity, thereby forming intriguing transport anisotropy. In this article, using extensive numerical simulations, it is found that this anisotropy introduces anomalous current transport behavior in vdW-based electron devices in which the current conducts in both the in-plane and cross-plane directions, including stacked heterojunction diodes and thin-film transistors (TFTs). Our study reveals for the first time that transport anisotropy degrades the performance of these devices, especially when devices are scaled (< 0.6μm) and/or relatively thicker materials (>4 nm) are used. Potential solutions to alleviate degradation are discussed as well. [ABSTRACT FROM AUTHOR]

An electrical transient model (ETM) of insulated-gate bipolar transistor (IGBT)-diode switching cell is developed by coupling a temperature-dependent IGBT model with power loss model. The nonlinear behavior of IGBT and the reverse recovery characteristic of the diode are considered in this model to simulate the transient switching waveforms. Based on the transient waveforms of ETM under various operating conditions, the power loss estimation method (PLEM) for IGBT is developed. In addition to traditional modeling techniques that only uses ideal switch, this paper uses the model to replicate the power loss behaviors of semiconductor devices in circuit simulation by looking up tables. The proposed ETM is simulated in PSCAD/EMTDC with nanosecond time step, whereas the overall system application can be simulated with conventional time step in range of microsecond. By this way, the model can promise reasonable accuracy as well as an acceptable fast solving speed. The proposed ETM and PLEM have been implemented in PSCAD/EMTDC simulator and validated by experimental results using a double pulse test bench and boost converter test platform. [ABSTRACT FROM AUTHOR]

Heavy-ion data suggest that a common mechanism is responsible for single-event burnout (SEB) in 1200-V power MOSFETs and junction barrier Schottky (JBS) diodes. Similarly, heavy-ion data suggest a common mechanism is also responsible for leakage current degradation in both devices. This mechanism, based on ion-induced, highly localized energy pulses, is demonstrated in simulations and shown to be capable of causing degradation and SEB for both the MOSFETs and JBS diodes. [ABSTRACT FROM AUTHOR]

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the K-band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified. [ABSTRACT FROM AUTHOR]

This article provides an understanding of the transient voltage overshoot physics observed with electro-static discharge (ESD) n-type, p-type, and n-type diffusions (NPN) bipolar devices through the use of calibrated technical computer-aided design (TCAD) with measured silicon results. This analysis graphically steps through each stage of the measured transient electrical response, to explain the inertia that limits the speed of the NPN ESD cell, and then uses this knowledge to provide a fully characterized silicon solution for ultrafast ESD events to achieve an 8-kV IEC61000-4-4 rating. This solution is developed by exploring five different integrated designs that are constructed on an 80-V bipolar and complimentary double-diffused metal-oxide semiconductor (BiCDMOS) process platform to protect against a product level 125-V voltage overshoot gate oxide ruptures as measured with a 0.6-ns rise time transmission line pulse (TLP). The fully characterized electrical results for each test overshoot structure with a fixed layout area of $200\,\,\mu \text{m}\,\,\times200\,\,\mu \text{m}$ , are in parallel to NPN ESD cells arranged with two in series and two in parallel ($200\,\,\mu \text{m}\,\,\times 80\,\,\mu \text{m}$) and compared in terms of the current-carrying capability before the gate oxide rupture voltage of 125 V is reached. The results show that a diode engineered with a vertical breakdown achieves an ESD strength of 9.7 A before the overshoot voltage reaches the target of 125-V, resulting in a net 0.17 mA $\mu \text{m}^{-{2}}$. The combined use of this vertical diode structure in parallel to the NPN ESD cell translates into a 7-A improvement in the strength of a conventional NPN for ultrafast timescales, which achieves the 8-kV International Electrotechnical Commission (IEC) ESD performance for this case study. [ABSTRACT FROM AUTHOR]

This letter presents a wide dynamic range low power consumption power detector with a compact area in a 65-nm complementary metal-oxide-semiconductor (CMOS) process. The maximum detectable power of traditional power detector is limited due to the non-linearity of mosfets. This problem is solved by using P-type and N-type doped material (PN) junction diodes as switches that have a linear input–output voltage relationship in the proposed power detector. In this structure, the switches work at both the positive and negative cycles to increase the dynamic range. With the increase of input power, the difference between the voltages applied to the two terminals of the diode is also increased. Thus, the current flowing through the diodes and the load resistor is augmented, boosting the output dc voltage. According to the measurement results, the power detector operates from 4 to ${\text{6 GHz}}$ with a dynamic range of 34 and $\pm {\text{1 dB}}$ error at ${\text{5 GHz}}$. To the authors’ best knowledge, it is the first power detector that has achieved such wide dynamic range with maximum input power of ${\text{35 dBm}}$. The core of the power detector occupies an area of ${\text{0.0036 mm}}^{2}$ and consumes 0.7-mW static power. [ABSTRACT FROM AUTHOR]

In this paper, alternative operational mode (AOM) of Si-based blocked impurity band (BIB) detectors is thoroughly investigated. The basic structure of the detector evolves from the prototype of the ion-implanted BIB detector, which is potentially compatible with CMOS processes. Benefiting from lower dark current, the detectivity of ion-implanted devices studied in this work is comparable with the Si BIB detectors ever reported. For ion implantation devices, a peak blackbody detectivity of ${5} \times {10}^{{12}}$ cm $\cdot $ Hz1/2/W (background temperature T = 40 K) occurs at 2 V under AOM. These merits make the ion-implanted device a powerful candidate for a wide range of applications from infrared to terahertz band. By analyzing the carrier distribution and the band structure in different functional regions of the device at the measured temperature, depletion junction formed in the region of active layer near active layer/cathode interface side is deduced when the device is operated under AOM. The theory is successfully used to interpret experimental data, including the detectivity comparable to the epitaxial device, significantly reduced dark current. [ABSTRACT FROM AUTHOR]

We present a circuit-design compatible large-signal compact model of metal–insulator–graphene (MIG) diodes for describing its dynamic response for the first time. The model essentially consists of a voltage-dependent diode intrinsic capacitance coupled with a static voltage-dependent current source, and the latter accounts for the vertical electron transport from/toward graphene, which has been modeled by means of the Dirac-thermionic electron transport theory through the insulator barrier. Importantly, the image force effect has been found to play a key role in determining the barrier height, so it has been incorporated into the model accordingly. The resulting model has been implemented in Verilog-A to be used in the existing circuit simulators and benchmarked against an experimental 6-nm TiO2 barrier MIG diode working as a power detector. [ABSTRACT FROM AUTHOR]

In this paper, a novel microwave power detection system based on Schottky diode is constructed in order to measure microwave power in the LTE-band (1.8~2.7 GHz). The proposed detection system is consisted of three modules: a collecting module, a measuring module, and a processing module. Among them, a microwave power detection circuit based on Schottky diode is developed to realize the high-quality conversion of microwave power signal to voltage signal. The experimental results reveal that the presented system has good linearity. In the range of 1.8~2.7 GHz, the incident microwave power is increased from 1 uW to 50 mW, and the sensitivity of the detection system is 1.86 mV/uW at 2.0 GHz, 1.61 mV/uW at 2.3 GHz, and 1.2 mV/uW at 2.6 GHz, which is much better than other microwave power sensors. Therefore, the microwave power detection system based on Schottky diode provides an effective solution for microwave power detection in the LTE-band. [ABSTRACT FROM AUTHOR]

This paper reports the design, fabrication, and test of a 3-D integrated uncooled focal plane array (FPA) using monocrystalline silicon diodes as thermosensitive devices. The diode array is fabricated from the silicon device layer of a silicon-on-insulator wafer, and the readout integrated circuits (ROICs) are fabricated on a bulk wafer using the CMOS technology. The silicon diode array is vertically integrated with the ROIC using the 3-D integration technology. Electroless nickel (Ni) plating is developed for fabricating substantial Ni posts to mechanically support the diode pixels to suspension and electrically connect the diode pixels to the ROIC. It allows the integration of monocrystalline device arrays with CMOS circuits fabricated using separate technologies and wafers in vertically suspended configuration. It also improves the filling factors of the FPA chips, shortens the wires between the diodes and the ROIC, and facilitates the releasing process to suspend the diode array. A $160 \times 120$ small-scale FPA has been developed as a test vehicle for concept verification. The test results and successful thermal imaging demonstrate the feasibility of the 3-D integration technology and verify the application of 3-D integration in the development of integrated FPAs using monocrystalline thermosensitive devices. [ABSTRACT FROM AUTHOR]

In this letter, we present for the first time a mixer circuit based on Metal–Insulator–Graphene (MIG) diodes fabricated with large-scale monolayer graphene grown by chemical vapor deposition. A small-signal model extracted from the diode physical structure is used together with a large-signal model extracted from the dc characteristics of the MIG diode to build a down-conversion mixer. The measured conversion loss at a local oscillator power ( ${P}_{\text {LO}}$ ) of 5 dBm is lower than 15 dB, while RF-to-IF isolation is 36 dB with an input return loss and RF-to-LO isolation better than 10 dB over the frequency band from 1.7–6 GHz. Promising mixer results in combination with the CVD-based process promote the MIG diode-based mixer to be used in low-power, low-cost, microwave, and millimeter-wave circuit applications. [ABSTRACT FROM AUTHOR]

In this letter, a functional Z2-FET DRAM memory matrix is experimentally demonstrated for the first time. Word-level operation with simultaneous reading and programming accesses is successfully proved. Disturbance is also explored, and the results demonstrate bitline disturbance immunity. Furthermore, the fabricated memory matrix, which includes only one selector per word-line, facilitates the scalability of the memory for increasing array dimensions. [ABSTRACT FROM AUTHOR]