38 results on '"Deguchi, T"'
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2. Colaborative Activities of Layered Neural Network.
3. On Memory Capacity in Incremental Learning with Appropriate Refractoriness and Weight Increment.
4. Error Correction Capability in Chaotic Neural Networks.
5. Poly-width-modification method for canceling layout-dependent characteristic variations for low-standby-power CMOS technologies.
6. Monitoring of mining induced land subsidence using L- and C-band SAR interferometry.
7. Layered neural networks computations.
8. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer.
9. Ka-band planar Gunn oscillators using flip-chip GaAs Gunn diodes fabricated by boron ion implantation.
10. Low-power high-speed ECL circuit with 0.5- mu m rule and 30-GHz f/sub T/ technology.
11. Novel selective poly - and epitaxial - Silicon growth (SPEG) technique for ULSI processing.
12. Neural network analysis of structural damage due to corrosion.
13. A performance-driven global routing algorithm with wire-sizing and buffer-insertion.
14. An ECL gate array with Si HBTs.
15. A 100 k-gate ECL standard-cell LSI with layout system
16. Relation between Groove Shape and Signal Quality in Magneto-Optical Disks.
17. Advanced bipolar process using selective poly- and epitaxial-Si (SPEG) technique.
18. Measurement of Disjoining Pressure of a Molecularly Thin Lubricant Film by Using a Microfabric ated Groove.
19. Relation between Signal Quality and Groove Shape in Magneto-Optical Disk(2).
20. Recording Characteristics of Magneto-Optical Disk with Quadrilayer Structure.
21. Search time of cyclic patterns in chaotic neural network
22. Two-stage filters for canceling a one-dimensional duct noise based on transmission-line model
23. 77 GHz planar Gunn VCOs on AlN substrates using novel flip-chip InP Gunn diodes
24. Layered Neural Networks Computations
25. Control of memory search by matching features with presynaptic inhibition
26. Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer
27. Ka-band planar Gunn oscillators using flip-chip GaAs Gunn diodes fabricated by boron ion implantation
28. A performance-driven global routing algorithm with wire-sizing and buffer-insertion
29. High-Performance E-Mode AlGaN/GaN HEMTs with LT-GaN Cap Layer Using Gate Recess Techniques.
30. A low-phase-noise 76-GHz planar Gunn VCO using flip-chip bonding technology.
31. Fabrication of timing extraction circuit integrating photodetector and SAW filter on piezoelectric substrate.
32. Search time of cyclic patterns in chaotic neural network.
33. 77 GHz planar Gunn VCOs on AlN substrates using novel flip-chip InP Gunn diodes.
34. V-band planar Gunn oscillators and VCOs on AlN substrates using flip-chip bonding technology.
35. Developmental change in perception of clause boundaries by 6- and 10-month-old Japanese infants.
36. Word recognition by Japanese infants.
37. Control of memory search by matching features with presynaptic inhibition.
38. A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array.
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