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GE Research has developed a low-cost inertial MEMS process flow for navigation-grade inertial sensor fabrication called the ‘Polaris' process. With a total of six mask layers, GE Polaris features thick silicon on insulation (SOI) with a 20 to 200 µm device layer, 30:1 high aspect ratio etching, and wafer level vacuum sealing with through silicon via (TSV) technology. GE Polaris has demonstrated good TSV ohmic contact, good vacuum seal integrity, high wafer yield with good etch symmetry and uniformity, and proven navigation-grade performance with high temperature reliability. GE Polaris strives to provide the simplest MEMS PNT flow for quick prototyping and low-to-mid volume production.

Hand function rehabilitation is one of the most important aspects to improve the quality of life and independence for stroke survivors. Access to therapy is a key factor in one’s ability to perform rehabilitation exercises and recover motor function. The aim of this research is to show the viability of using a soft robotic glove to perform home-based rehabilitation of the hand function of stroke survivors. Soft wearable robotic devices are a promising approach to hand rehabilitation due to their lightweight, compliant, and low-cost design. The goal of this wearable technology is to reduce hyperexcitability of the flexor muscles through cyclic stretching of the fingers, active-assisted exercise, and task-oriented training. In this pilot study, four chronic stroke survivors were provided 300 repetitions of opening and closing their hand with the soft robotic glove over 6 training sessions. This high-intensity, high-repetition protocol was found to be safe and well-tolerated by all subjects. Results demonstrated average increases of 18.5° and 17.3° in the relaxed metacarpophalangeal and proximal interphalangeal joint angles, respectively, of the index finger and an average increase of 33 Newtons in grip strength. This work motivates further development of this home-based soft robotic rehabilitation device and lays the groundwork for a longer term study.

The orientation module of MWD tool provides the critical drill bit orientation information, including azimuth, inclination and toolface in order to control the path of wellbore. Although high end navigation grade gyroscope can meet the accuracy requirement for azimuth finding, the requirements of cost, size and reliability under harsh environment have largely limited the deployment of gyroscopes in MWD tools. To overcome these constraints, GE Research has developed a low cost, MEMS based Multi-Ring Gyroscope (MRG) capable of azimuth-seeking in MWD applications at 300°C. The MRG prototype has been demonstrated to achieve angular random walk (ARW) better than 0.003 deg/rt(hr) and bias instability of 0.01 deg/hr, capable of meeting azimuth finding accuracy better than 0.25 deg. It has also been tested to remain fully operational at 300 °C.

Monolithic three-dimensional (3D) integration provides the most fine-grained integration of transistors. Monolithic inter-tier vias (MIVs) used for inter-tier electrical connections in monolithic 3D integrated circuits (ICs) are as small as local vias, so parasitic resistance and capacitance of an MIV is much smaller than that of a through-silicon via (TSV). In addition, MIVs are much smaller than TSVs, so many MIVs can be inserted into a layout while enabling very high bandwidth between adjacent tiers. Thus, monolithic 3D ICs have been actively researched in the literature recently. In this paper, we proposes a gate composition algorithm to reduce the runtime for routing of monolithic 3D ICs. Simulation results show that the gate composition algorithm reduces the runtime by 11% to 76%.

The concept of smart home technology has become more common in modern homes and has allowed for detailed monitoring of many household aspects. Data collected around the home, such as energy usage and waste produced, can be used to make daily life more convenient and create a more energy efficient household. The purpose of this project was to create a series of sensors to monitor a house that functions as an Internet of Things (IoT). This was accomplished through the development of a temperature/humidity sensor, door motion sensor, light sensor, and color sensor. These sensors were chosen to monitor the characteristics of a hypothetical house, so a program could give suggestions for conserving energy. The house monitoring system was built out of Arduino microcontrollers and a Java graphical user interface (GUI). The values taken from these sensors are compiled in a central computing source which adjusts air conditioning (AC) or sends alerts to the user based on the data collected around the home. The sensors are also linked through Bluetooth to create a fully functional household IoT. This sensor system aims to eliminate wasted energy and money by creating an automated system to efficiently regulate a home.

This paper describes engineering analysis and experimental evaluations used to design an innovative imbedded cooling concept for RF thermal management. The concept, called Impingement Cooled Embedded Diamond (ICED), uses liquid flowing through diamond-lined microchannels etched into the back of a GaN-on-SiC RF die to manage heat produced by the transistors. This approach combines the superior heat spreading of high-conductivity diamond with the outstanding convection capability of impinging jets to manage local heat fluxes as high as 30 kW/cm2. The first part of this paper presents the CFD analysis used to design the microfluidics, select diamond thickness, and understand the sensitivity of performance to component assembly, coolant temperature and composition, and channel dimensions. It also describes the structural analysis used to evaluate ICED mechanical stress levels, including those imposed by diamond growth and hardware assembly. The second part of this paper presents experimental measurements performed to validate the computer models and demonstrate the thermal management capability of the proposed design. These experiments confirmed the effectiveness of the impinging jets at drawing heat produced by the transistors directly to the coolant, reducing transistor mutual heating and enabling a four-fold increase in expected RF output power. They also showed the proposed cooling concept mitigates self-heating thermal limitations and enables aggressive design compaction not possible with existing conduction GaN-on-SiC cooling solutions.

Monolithic three-dimensional (3D) integration enables the most fine-grained integration of transistors by stacking very thin layers and fabricating monolithic inter-layer vias as small as local vias. Thus, monolithic 3D integration is expected to provide a higher degree of wirelength reduction, performance improvement, and power saving. Due to the prospective properties of the monolithic 3D integration technology, research on multilayer monolithic 3D integration that stacks more than two device layers is also ongoing. In this paper, we propose an algorithm that optimizes dynamic power consumption of gate-level monolithic 3D ICs. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than a uniform-scaling-based placement algorithm. We also design multi-tier monolithic 3D ICs and show that our algorithm outperforms the uniform-scaling-based placement algorithm by 11.4% on average.

The focus of this work is on measuring and classifying human micro-Doppler features in forested environments. As a first step, measurements of human motion activities are performed in an open space environment to establish the baseline of this study. Next, forest measurements were taken at two locations in a local park for: different frequencies, activities, and number of subjects. Each experimental trial was measured for 20 seconds using a vector network analyzer (VNA) and post-processed into spectrograms, from which features are extracted to classify human motion activities.

During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a coordinated fashion: 1. Quick Error Detection (QED) tests that quickly detect bugs with short error detection latencies and high coverage. 2. Formal analysis techniques to localize bugs and generate minimal-length bug traces upon detection of the corresponding bugs. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using "difficult" logic bug scenarios that occurred in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic (unlike manual techniques in use today that can be extremely time-consuming and expensive); (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques; and, (iv) does not require any additional hardware.

The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integrity, a low-latency, high-throughput on-chip network (OCN), a database analytic accelerator (DAX), fine-grain adaptive power management and 1.5× higher SerDes I/O bandwidth for memory, coherency and system interfaces (Fig. 4.2.1) [1]. The enhancements in the S4 core over the S3 core [2] include a new L2 cache scheme, support for visual instruction set (VIS) extensions, virtual address masking and user-level synchronization instructions to provide continuous single-thread performance improvement for SPARC processors since SPARC T4. In addition, a hierarchical modular approach, called SPARC cache cluster (SCC), is used for the core-L2-L3 cache system. Within the SCC, all four cores share a single 256KB L2 instruction cache and each core pair has its own 256KB L2 data cache. The L2 caches are organized as 2-banks and 8-ways to deliver greater than 1TB/s bandwidth to the four cores. This L2 system delivers 2× more throughput for each core with 1.5x increase in size and the same latency as the previous generation L2 cache scheme. The L2 caches connect to an 8MB, 8-way set-associative partitioned L3 cache. Having a localized L3 cache within each SCC reduces L3 latency by 25%. The chip contains eight SCCs for a total of 32-cores with 256 threads and a 64MB L3 cache with 1.6TB/S bandwidth. In order to support the bandwidth and latency requirements from 256 threads and other system agents, the OCN architecture is implemented in place of a crossbar based network used in previous SPARC processors. Each SCC connects to the OCN, which in turn connects to four on-chip memory controllers (MCUs), coherency systems and eight database analytic accelerator (DAX) engines. The SPARC M7 introduces a customized DAX engine in an effort to optimize performance for Oracle databases. Eight DAX engines handle simple query predicates, decompression, message passing and interrupts across cluster nodes. This query accelerator provides up to 10x better performance for single stream decompression.

This paper presents the Quick Error Detection (QED) technique for systematically creating families of postsilicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory controllers, on-chip interconnection networks) of multi-core System on Chips (SoCs). Such quick detection is essential because long error detection latency, the time elapsed between the occurrence of an error due to a bug and its manifestation as an observable failure, severely limits the effectiveness of traditional post-silicon validation approaches. QED can be implemented completely in software, without any hardware modification. Hence, it is readily applicable to existing designs. Results using multiple hardware platforms, including the Intel® Core™ i7 SoC, and a state-of-the-art commercial multi-core SoC, along with simulation results using an OpenSPARC T2-like multi-core SoC with bug scenarios from commercial multi-core SoCs demonstrate: 1. Error detection latencies of post-silicon validation tests can be very long, up to billions of clock cycles, especially for bugs inside uncore components. 2. QED shortens error detection latencies by up to 9 orders of magnitude to only a few hundred cycles for most bug scenarios. 3. QED enables up to a 4-fold increase in bug coverage.

During post-silicon validation and debug, one or more manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). According to several industrial reports, the costs of post-silicon validation and debug are rising faster than design costs. Hence, new techniques are essential to reverse this trend. QED, an acronym for Quick Error Detection, is such a technique that effectively overcomes several post-silicon validation and debug challenges. QED systematically creates a wide variety of validation tests to quickly detect bugs, not only inside processor cores, but also inside uncore components (i.e., components in an SoC that are neither processor cores nor coprocessors) of multi-core SoCs. In this paper, we present a brief overview of QED through a series of frequently asked questions.

This paper describes a convection-based, self-contained heat spreader that provides device-level thermal management for GaN power amplifiers. The concept connects microchannels etched into the backside of the die to a liquid flow circuit that includes autonomous flow-balancing valves, a diaphragm pump, and a high-performance heat exchanger. The integrated system provides a heat spreading capability that reduces transistor gate heat fluxes by up to four orders of magnitude, enabling device-level temperature control using conventional cold plates. This paper will review the analysis used to design the key components in the assembly and to project their performance as part of an integrated system.

This paper describes our third generation multicore processor that exhibits a high level of integration [1]. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over [1]. It contains 700M transistors and has been fabricated in a 65nm process technology, with 10 layers of copper interconnect and C4 bumps. It contains 32 MIPS cores, 4MB of level 2 cache, multiple hardware accelerator units, 4 72b DDR3 memory controllers operating at 1600 MHz, 20 generic SerDes lanes up to 6.25Gb/s, additional network and boot interfaces and general purpose I/Os. Maximum frequency is 1.6GHz for cores and L2 cache. Excluding I/O, thermal design power ranges from 40W to 65W depending on the frequency bin.

Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Existing post-silicon validation methods barely cope with today's complexity. New techniques are essential to minimize the effects of bugs and design flaws going forward. This talk will focus on two recent techniques, QED and IFRA, that can overcome significant challenges associated with a very crucial step in post-silicon validation: bug localization in a system setup. We demonstrate the effectiveness of these techniques using results from quad-core Intel Core i7 hardware platforms and Intel Nehalem processors, and using actual examples of “difficult” bugs that occurred in complex SoCs.

The paper presents a novel approach to evaluate and improve MEMS reliability even during design phase of new devices. Firstly, the shock induced failure mechanisms of breakage and stiction are characterized by test structures. The obtained results in terms of maximum rated loads are compared to acting loads during the actual mechanical shock, which are calculated by a numerical impact model. The model is based on the modal superposition approach and can be applied to arbitrary designs. It accounts for impacts at flexible travel stops including stiction as well as for large structural deflections leading to strongly nonlinear squeeze damping.

As part of the reliability investigation, shock tests for first generation surface micro-machined devices have been performed which showed susceptibility regarding stiction at the stopper elements and breakage of adjacent anchor points to the substrate. This paper clearly demonstrates how the application of compliant travel stops can solve these issues but it also points out limitations of this approach. A numerical model has been developed to help understand the events during a shock load and the working principle of compliant stops. Compared to the previous work of Yoon et al. [1–3], this investigation gives a practical guideline regarding application and dimensioning of flexible stops and adjacent anchors at MEMS products where available design space is limited and structural deflections are restricted. Furthermore, it gives the possibility to take viscous damping and different pulse shapes as well as durations into account.

Long error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as a system-level failure, is a major challenge in post-silicon validation of robust systems. In this paper, we present a new technique called Quick Error Detection (QED), which transforms existing post-silicon validation tests into new validation tests that significantly reduce error detection latency. QED transformations allow flexible tradeoffs between error detection latency, coverage, and complexity, and can be implemented in software with little or no hardware changes. Results obtained from hardware experiments on quad-core Intel® Core™ i7 hardware platforms and from simulations on a multi-core MIPS processor design demonstrate that: 1. QED significantly improves error detection latencies by six orders of magnitude, i.e., from billions of cycles to a few thousand cycles or less. 2. QED transformations do not degrade the coverage of validation tests as estimated empirically by measuring the maximum operating frequencies over a wide range of operating voltage points. 3. QED tests improve coverage by detecting errors that escape the original non-QED tests.

New generations of video, voice, high-performance computing and social networking applications have continuously driven the development of novel routing technologies for higher packet forwarding speeds to meet the future Internet demand. One of the fundamental design issues for core routers is fast routing table lookup, which is a key problem at the network layer of the Internet protocol suite. It is difficult to scale the current TCAM-based or trie-based solutions for future routing tables due to increasing table size, longer prefix length, and demands for higher throughput. This paper focuses on hash-based lookup solutions that have the potential of offering high throughput at one memory access per packet. We design the first deterministic multi-hashing scheme with small indexing overhead, which evenly distributes address prefixes to hash buckets for routing-information storage. We minimize both the size of each bucket and the number of buckets that need to be fetched to the network processor for packet forwarding. Consequently, near-optimal routing throughput is achieved. Performance evaluations demonstrate that the proposed deterministic multi-hashing scheme can maintain a constant lookup rate of over 250 million packets per second with today's commodity SRAM, which is much faster than the existing hashing schemes.

The paper is focused on the influence of packaging technologies on the performance of inertial MEMS sensors. System simulations of MEMS are vital to evaluate and optimize the interplay of transducer cells with the sensor electronics. Special emphasis must be put on packaging aspects in order to assess the impact of environmental and operating conditions on functional parameters as capacitance offset or loss of sensitivity affected by thermal-mechanical stress or structural deformation. This article presents modern reduced order modeling technologies which extract fast and accurate behavioral models from a series of finite element runs which can directly be used in Matlab/Simulink or Verilog-A for system design.

In this paper we use the mechanisms of a popular bottom-up computational model of visual attention in order to evaluate the gaze patterns of individuals in terms of elementary modalities such as color, orientation, motion, and intensity. We show that children with autism, even when watching naturalistic scenes, use less motion information, extending basic perceptual findings of motion deficits in autism to real-world scenes. In addition, by modifying the context of videos shown to children with and without autism (by changing the video scene, inverting the video, and displaying the video with and without sound) we show that that typical children, as compared to children with autism, are more affected by scene inversion. We discuss these and other results in terms of known sensory and cognitive abnormalities in autism and highlight the advantages and limitations of computational strategies in evaluating the effects of context on perceptual utilization.

In this work, homomorphic image modeling is used to make the exhaustive block-matching algorithm (EBMA) more human vision system (HVS) aware, thus yielding visually pleasing sequences. Homomorphic signal processing is used to separate the luminous and the structural components of each frame; EBMA is then applied to both components to capture the luminous and the structural changes. The combination of these two techniques is utilized to simulate the structure preserving nature of HVS. Temporal irrelevancies are reduced by removing the excess motion fields from both components. The homomorphic EBMA (H-EBMA) processed sequences have superior visual quality despite mean PSNR values that are comparable to sequences produced by traditional EBMA.

Many studies have many studies have been conducted using ATM technology to implement B-ISDN. These have shown that ATM virtual path (VP) technology, due to its fast cross-connect system, can be used to achieve rapid restoration for a distributed control mesh-type restoration system. The signaling channel using operations and maintenance (OAM) cells further improves restoration time because of the high bandwidth available to the OAM cells in an ATM VP network. Within the framework of logical channel protection scheme, self-healing restoration can be provided at two different schemes: path restoration and line restoration. Path restoration restores the end to end logical channel (i.e. finds an alternative logical channel), and line restoration restores demands carried by the failed link. We propose a new three-phase distributed VP self-healing scheme using path restoration protocol to achieve high restoration ratio, with an average restoration time of around 1-second, and less spare capacity assignments due to more efficient usage of them in the network. An empirical study based on a real metropolitan LATA mesh network shows that, under the condition of assigning sufficient VPs between the same source and destination, the three-phase path restoration protocol has superior performance compare to the existing two-phase line restoration protocol over a number of networks with randomly generated VP assignments and spare capacity assignments. This empirical study also shows that restoration times of the proposed path restoration protocol are mostly around 1 second which is well suited for metropolitan LATA mesh networks.