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International audience; Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this article has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation. On the other hand, it describes the implementation of a robotic arm controller based on the DLS to numerically solve Inverse Kinematics problems over a heterogeneous FPGA. Assessments involve a Trossen Robotics WidowX robotic arm controlled by a Digilent ZedBoard provided with a Xilinx Zynq FPGA that computes the Inverse Kinematic.

In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS $0.18~\mu m$ technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is $5.9 mm \times 5.9 mm$ , and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

As AI-based applications become pervasive, CPU vendors are starting to incorporate matrix engines within the datapath to boost efficiency. Systolic arrays have been the premier architectural choice as matrix engines in offload accelerators. However, we demonstrate that incorporating them inside CPUs can introduce under-utilization and stalls due to limited register storage to amortize the fill and drain times of the array. To address this, we propose RASA, Register-Aware Systolic Array. We develop techniques to divide an execution stage into several sub-stages and overlap instructions to hide overheads and run them concurrently. RASA-based designs improve performance significantly with negligible area and power overhead., This paper is accepted to DAC 2021

Posit arithmetic has better dynamic range and accuracy over the conventional IEEE-754 floating-point. In this paper, architectures for posit adder/subtractor and multiplier have been proposed that work as per the desired bit size of operands. Here, 16 and 32-bit architectures with different exponent size (ES) have been designed. FPGA implementations of these architectures have been done on the Xilinx Virtex-7 xc7vx330t-3ffg1157 device. In comparison with existing work, it has been observed that the usage of LUTs with ES=2 is lowered by 7.11/16.07% for 16/32-bit adders, and 1.81% for 32-bit multiplier with ES=3. In addition, 16/32-bit adder architectures require 31.47/31.66% lesser datapath delay. The 16/32-bit posit multipliers consume 10.40/10.84% lesser delay.

Simultaneous multithreading (SMT) processors target resource under-utilization related performance problems of superscalar processors by allowing various datapath resources to be simultaneously shared among several threads with ease. This approach exploits thread-level parallelism on top of the well-studied instruction level parallelism. However, when datapath resources are shared among threads, there is always a possibility that corunning ill-intended programs may try to sniff on other programs with sensitive information like passwords or cryptocurrency information. By stress-testing and measuring many of the shared resources, this is quite achievable. These approaches are known as side-channel attacks. SMT-COP, a study published recently, is a secure architectural implementation based on resource scheduling that prevents these kind of attacks based on execution logic with a modest performance loss of nearly 10%. In this study, we aim to improve SMT-COP’s resource distribution scheme with several approaches, providing a quite close sense of security to that of SMT-COP while improving the performance by up to 8.86% on the average, over the original SMT-COP design.

The SMT (Simultaneous Multithreading) architecture is widely used in modern processors. It provides a performance gain in the system by running multiple threads simultaneously to better utilize datapath resources. In this architecture, one of the research areas is how to allocate common resources among threads. In the static approach, resources are allocated to threads equally or according to a specific predefined rule. In the dynamic approach, monitoring the system at runtime, the most appropriate allocation strategy is chosen. Hill-Climbing and Stretch are two examples of dynamic resource allocation methods. This paper proposes a hybrid approach that combines Stretch with the Hill-climbing method to improve both the throughput and the QoS metrics of the SMT processor. We compare our QoS-Oriented and Throughput-Oriented methods, showing that we can satisfy a target QoS on a latency-sensitive thread, while still achieving near-optimal (only an average of 0.6% worst performance over the Throughput-Oriented method) throughput with our QoS-Oriented approach.

In this paper, a very compact architecture the newest member of the SNOW family of stream ciphers, called SNOW-V, is presented. The proposed architecture has a 128-bit datapath and is pipelined in key areas in order to achieve the maximum possible frequency while using only a small number of hardware resources. The design was coded using the VERILOG hardware description language and the BASYS3 board (Artix 7 XC7A35T) was the target of the hardware implementation. The proposed implementation utilizes only 2109 FPGA LUTs and 1352 FFs and reaches a data throughput of 2.6 Gbps at 224 MHz clock frequency.

”Soft” GPUs are overlays that implement GPGPU-like data parallel processor architectures in FPGA logic to make FPGAs as software-programmable as ”hard” GPGPUs. Unlike hard GPUs, soft GPU architectures can be specialized to further improve efficiency by leveraging FPGA’s flexibility. Prior work has shown the software programmability potential for soft GPUs but only studied general-purpose soft GPUs with minor specializations (e.g., FPGU, FlexGrip, MIAOW, and SCRATCH) or only domain-optimized for a particular application domain (e.g., PDL-FGPU for the persistent deep learning domain.) This paper proposes a soft GPU development framework to automate the creation of soft GPU instances with aggressive application-domain optimizations (i.e., domain-optimized GPUs, or DOGPUs) that consists of a baseline general soft GPU architecture ”template” with an improved architecture over prior general purpose soft GPUs, along with a customizable partition that enables a custom datapath (macro unit) to be inserted to optimize for a target application domain. Unlike the prior PDL-FGPU which targets the persistent deep learning domain, the proposed framework can be used to target optimization for any application domain. Our evaluation on a set of data parallel workloads shows that (i) the proposed general soft GPU architecture offers average speedup of 1.8x versus the best prior soft GPUs we know of (i.e., FGPU, PDL-FGPU), (ii) DO-GPUs with domain-optimizations provide an average of 218x speedup over general soft GPUs, (iii) the proposed framework enabled building six new domain-optimized soft GPU instances in a matter of days, and (iv) enables quick GPU-like development effort (hours), where code is concise (low 100s of lines) and can be compiled in seconds without FPGA EDA tools in the loop, assuming an appropriate soft DO-GPU bitstream for the application domain is already built.

Deep neural networks (DNNs) are vulnerable to maliciously generated adversarial examples. These examples are intentionally designed by making imperceptible perturbations and often mislead a DNN into making an incorrect prediction. This phenomenon means that there is significant risk in applying DNNs to safety-critical applications, such as driverless cars. To address this issue, we present a visual analytics approach to explain the primary cause of the wrong predictions introduced by adversarial examples. The key is to analyze the datapaths of the adversarial examples and compare them with those of the normal examples. A datapath is a group of critical neurons and their connections. To this end, we formulate the datapath extraction as a subset selection problem and approximately solve it based on back-propagation. A multi-level visualization consisting of a segmented DAG (layer level), an Euler diagram (feature map level), and a heat map (neuron level), has been designed to help experts investigate datapaths from the high-level layers to the detailed neuron activations. Two case studies are conducted that demonstrate the promise of our approach in support of explaining the working mechanism of adversarial examples.

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 μm CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB., FRCT - Fundo Regional para a Ciência e Tecnologia(PDE/BDE/114562/2016)

The end of Moore's law and the arrival of new highly demanding applications have awakened the interest in exploring different number representation formats and also combining them to implement domain-specific accelerators. Typically used in DSP applications, word-length optimization (WLO) allows finding the optimum combination of word-lengths for each signal on a circuit for a given error threshold. In the optimization process, for any word-length combination, the error has to be estimated or computed by bit-true simulation. The latter is widely used since it can be applied to any type of system. However, simulation is very time-consuming, and the WLO becomes an extremely long process. This paper proposes a methodology based on a WLO-wise hardware architecture that speeds up WLO significantly. In our approach, the target datapath is implemented on an FPGA with a “precision limiter” on each selected signal. This architecture allows performing bit-true emulation on the FPGA for any given word-length combination without reconfiguring the FPGA; just configuring the limiters, which is a much faster process.

Large persistent memories such as NVDIMM have been perceived as a disruptive memory technology, because they can maintain the state of a system even after a power failure and allow the system to recover quickly. However, overheads incurred by a heavy software-stack intervention seriously negate the benefits of such memories. First, to significantly reduce the software stack overheads, we propose HAMS, a hardware auto-mated Memory-over-Storage (MoS) solution. Specifically, HAMS aggregates the capacity of NVDIMM and ultra-low latency flash archives (ULL-Flash) into a single large memory space, which can be used as a working memory expansion or persistent memory expansion, in an OS-transparent manner. HAMS resides in the memory controller hub and manages its MoS address pool over conventional DDR and NVMe interfaces; it employs a simple hardware cache to serve all the memory requests from the host MMU after mapping the storage space of ULL-Flash to the memory space of NVDIMM. Second, to make HAMS more energy-efficient and reliable, we propose an "advanced HAMS" which removes unnecessary data transfers between NVDIMM and ULL-Flash after optimizing the datapath and hardware modules of HAMS. This approach unleashes the ULL-Flash and its NVMe controller from the storage box and directly connects the HAMS datapath to NVDIMM over the conventional DDR4 interface. Our evaluations show that HAMS and advanced HAMS can offer 97% and 119% higher system performance than a software-based NVDIMM design, while costing 41% and 45% lower energy, respectively.

This paper describes a scalable, highly portable, and power-efficient generator for massive multiple-input multiple-output (MIMO) uplink baseband processing. This generator is written in Chisel, and produces hardware instances for the distributed processing in a scalable massive MIMO system. The generator is parameterized in both the MIMO system and hardware datapath elements. The performance of several generator instances with different parameter values are validated by emulation on a field-programmable gate array (FPGA), demonstrating both functionality and scalability, and operation up to 6.4Gb/s data throughput.

Most of the terminal nodes for information and telecommunication networks are developed using ASIC technology. Compared to FPGAs, it allows for lower power consumption and smaller area (size). However, in order for production to be profitable, chips must be produced in fairly large series - from several hundred copies. Because of this, terminal nodes must be universal enough to provide the ability to use them in networks for various purposes with different structures and architectures, different distributed computing schemes, with various rules of interaction between tasks, and with different memory architectures. Accordingly, networks may use different transport layer protocols. Additional actions in the interaction between the transport and application layers may be required in terminal nodes. Different schemes can be used to interact with memory, for example, Open MPI, MPICH, etc. To ensure performance in working with memory, it is very important that the corresponding scheme for interacting with memory is supported at the transport protocol level. Terminal nodes can be operated for several years. During this time period, new versions of transport protocols can be developed that are more suitable for the tasks being solved. It is very important that terminal nodes provide this new | universal functionality without replacing equipment. The transport controller unit must be dynamically reconfigurable to meet these requirements. Today, dynamically reconfigurable components are typically designed with using Field Programmable Gate Array (FPGA). However, the power consumption, area, timing characteristics (for example, the achievable clock frequency) of FPGA implementations are significantly worse than the same parameters of the implementations with using ASIC. These factors significantly limit the field of application of dynamically reconfigurable systems based on FPGAs. In previous works, we proposed an approach to the development of a dynamically reconfigurable transport protocol controller based on a dynamically reconfigurable automata and a dynamically reconfigurable DataPath. In this paper, we propose an approach to the development of a dynamically reconfigurable transport layer controller based on a processor core with RISC- V architecture. The paper presents several examples of using the proposed approach. We estimated the achievable parameters and overheads for these examples using a reconfigurable automata and reconfigurable DataPAth implementation and using a RISC-V based implementation.

Programmable controllers (PLCs) were developed to solve the problems of automating and manufacturing control systems and they have found wide applications in industrial control fields. Ladder diagram is the most adopted programming language for PLC control. Process sequence and flow charts can be used for simple PLC ladder diagram design. For complex PLC controls, state diagrams have been proposed for PLC ladder diagram programming. However, state diagram method has some limitations. In this paper, based on the analysis and design techniques of digital systems, we proposed a new PLC design approach. In this method, first we need to identify the functions of datapath and controller and the inputs/outputs of both. Second, Algorithmic State Machine(ASM) charts are used to draw the state transitions for the controller. Finally, a ladder diagram is designed from the ASM chart. The best practices with this approach are also discussed in the paper.

This paper presents a new formal method for detecting and identifying hardware Trojans (HTs) inserted into the datapath of cryptographic hardware based on Galois-field arithmetic such as for the Advanced Encryption Standard and elliptic curve cryptography. To detect HTs, our method first performs equivalence checking between the specifications given as Galois-field polynomials (or the reference circuit of cryptographic hardware) and polynomials representing the input-output relations of a gate-level netlist. Our method exploits zero-suppressed binary decision diagrams for efficient verification. Once an HT is found, the proposed method then detects the trigger condition of the HT using the characteristics of zero-suppressed binary decision diagrams. It also identifies the HT localization using a novel computer algebra method. Our experimental results show that the proposed method can verify netlists and identify HT trigger conditions and locations on a 233-bit multiplier commonly used in elliptic curve cryptography within 1.8 seconds. In addition, we show that if the reference circuit is given, the proposed method can detect a realistic HT inserted into the entire Advanced Encryption Standard hardware, including control logic, in approximately three seconds.

In this paper, we present a novel Configurable Pipelined Datapath for custom Data Acquisition Systems (DASs) in the context of Interventional Computed Tomography (iCT). The introduction of new medical techniques during surgery results in a multitude of challenging requirements on the hardware architecture (e.g., real-time data processing, high data-rate, hard deadline on data acquisition and storage). Therefore, we propose a Pipelined Datapath for System-on-Chip FPGAs, that can be configured at design time and run time. It supports all data processing steps from the detector sensors’ data acquisition to the image-processing reconstruction system. It can be configured, depending on the CT physical limitations and the medical scenarios. Besides, the Pipelined Datapath avoids any buffering on off-chip memory, differently from other architectures in literature.

The distributed two-level control (D2LC) system has been adopted in streaming application accelerators that implement atomic vector operations. Each instruction of such architecture deals with one aspect (arithmetic, interconnect, storage, etc.) of an atomic vector operation. The D2LC architecture is different from traditional computer architecture such as MMX or VLIW. The D2LC architecture consists of many cells interconnected via a NoC. In each cell, there is a two-level controller. The level-1 controller sends instructions to configure their level-2 controllers. Each level-2 controller, once configured, works as an independent finite state machine (FSM). It manages a datapath for specific functionality, including computation, interconnection, as well as storage. We can say that the level-1 controllers implement threads while the level-2 controllers implement micro-threads. For generality, these microthreads, even though distributed in different cells, can be grouped by the interconnection units and orchestrated to implement a larger functionality. The compiler of D2LC architecture needs to schedule these micro-threads correctly so that the larger functionality is reached.

Deciding whether a faulty circuit can be rectified at a given set of nets to match its intended specification constitutes a critical problem in post-verification debugging and rectification. Contemporary approaches which utilize Boolean SAT and Craig Interpolation techniques are infeasible in proving the rectifiability of arithmetic circuits. This paper presents a novel approach using symbolic computer algebra to prove the rectifiability of a faulty finite field arithmetic circuit at a given set of m nets. Our approach uses a word-level polynomial model and an application of a Grobner basis decision procedure. The finite fields corresponding to the datapath word-length (n) and the patch word-length (m) may not be compatible. We make new mathematical and algorithmic contributions which resolve this disparity by modeling the problem in an appropriate composite field. Experiments demonstrate the efficacy of our word-level approach to ascertain multi-fix rectifiability compared to contemporary approaches.

Three-dimensional stack memory that provides both high-bandwidth access and large capacity is a promising technology for next-generation computer systems. While a large number of memory cubes increase the aggregate memory capacity, the communication latency and power consumption would become significant due to its low-radix large-diameter packet network. In this context, we propose a memory-cube network called Diagonal Memory Network (DMN). A diagonal network topology, its floor layout, and its lightweight router are designed for low-latency and low-voltage memory-read communication. Our evaluation results show that a DMN router decreases 31% of the hardware resources than a conventional virtual-channel router. The DMN router reduces 13% and 67% energy consumption to transit a packet along with the original datapath and bypassing datapath, respectively.

The paper presents an alternative Single-Event Effect (SEE)-tolerant Triple Modular Redundancy (TMR) circuit topology for space applications. The proposed D-flip-flop circuit scheme is fully digitally designed and consists of local Single Event Transient (SET) filter for transient mitigation on the datapath. A latch-based master-slave decomposition with the usage of commercially available unhardened standard cell components is selected. The baseline architecture and the proposed multi-row cell layout is briefly described. Corresponding shift register test vehicles are implemented in 0.13 µm BiCMOS technology. An SEE robustness of a selected candidate with an LET of 46.1 $\frac{\text{MeV} \cdot \text{cm}^{2}}{\text{mg}}$ is measured as a proof of concept.

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. Theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. Third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

As smart devices are developed, cryptography is one of the key points when designing the devices. ARIA has been developed in substitution for AES as a light-weight hardware implementation. As ARIA has four types of S-box, S-box hardware cost is high compared to AES. In this paper, we proposed key length reconfigurable ARIA architecture which operates on three kinds of key length 128/192/256-bit in one module. It is based on 8-bit datapath, thereby sharing multiplication inverse is possible that four kinds of S-box can be optimized. The proposed key length reconfigurable ARIA has been implemented using 65nm CMOS technology and it showed 16,822 gate counts. This result showed 23% area reduction compared to previous work.

This paper describes a scalable, highly portable, and energy-efficient generator for massive multiple-input multiple-output (MIMO) baseband processing systems. This generator is written in Chisel and produces hardware instances for a scalable massive MIMO system employing distributed processing. The generator is parameterized in both the MIMO system and hardware datapath elements. Coupled with a Python-based system simulator, the generator can be adapted to implement other baseband processing algorithms. To demonstrate the adaptability, several generator instances with different parameter values are evaluated by FPGA emulation. In addition, a beamspace calibration and channel denoising algorithm are applied to further improve the channel estimation performance. With those algorithms, the error vector magnitude can be reduced by up 9.2%., 2021 IEEE Workshop on Signal Processing Systems (SiPS), ISBN:978-1-6654-0144-9, ISBN:978-1-6654-0145-6

Data parallel applications frequently work with data elements whose width is less than the processor dathpath width. However, most processors do not support parallelism of multiple sub-width elements but rather expand them to the datapath width and process them in a sequential manner. In this paper, we propose a set of systematic divide and conquer approaches to design a fractured integer multiplier unit which allows for either a single datapath-width multiplication or multiple sub-width multiplications to be simultaneously executed. The supported integer width can be configured at runtime. We also evaluate and compare the proposed approaches demonstrating the advantages and disadvantages of each. Such fractured multipliers are particularly suitable for vector and multimedia processors.

Due to the rapid growth of using Internet of Things (IoT) devices in the daily life, the need to achieve an acceptable level of security and privacy according to the real security risks for these devices is rising. Security risks may include privacy threats like gaining sensitive information from a device, and authentication problems from counterfeit or cloned devices. It becomes more challenging to add strong security features to extremely constrained devices compared to battery operated devices that have more computational and storage capabilities. We propose a novel application specific instruction-set architecture that allows flexibility on many design levels and achieves the required security level for the Electronic Product Code (EPC) passive Radio Frequency Identification (RFID) tag device. Our solution moves a major design effort from hardware to software, which largely reduces the final unit cost. The proposed architecture can be implemented with 4,662 gate equivalent units (GEs) for 65 nm CMOS technology excluding the memory and the cryptographic units. The synthesis results fulfill the requirements of extremely constrained devices and allow the inclusion of cryptographic units into the datapath of the proposed application-specific instruction set processor (ASIP).

This paper presents a novel overlay-based approach for rapid in-circuit debugging and tuning of Deep Learning (DL) designs targeting Field-Programmable Gate Array (FPGA). We first propose overlay-based instruments designed to provide profiling information of hardware to builders of deep learning applications for tuning and debugging FPGA designs. Our instrumentation is optimized to take advantage of characteristics of DL application domain-specific information. We also implement a light-weight overlay-based Deep Neural Networks (DNN) processing engine that supports rapid word length tuning for each DNN layer's datapath without requiring time-consuming compilation of FPGA designs multiple times. Combining the overlay-based instrument and DNN processing engine together, we can visualize the patterns of overflow exceptions and support rapid mixed precision tuning of DNN layers on FPGAs.

Security is a concern in wireless sensor networks, which are inherently prone to third party attacks. As such, cryptography is used to make a secure mode of communication among nodes and/or between nodes and base stations. However, conventional algorithms are resource-hungry and therefore not fit for small devices, hence the creation of a new category of cryptography known as Lightweight Cryptographic Algorithms. These algorithms are still continuously being improved to fit in the decreasing sizes of small scale devices like FPGA-based wireless sensor networks. In this study, we quantify the effects of Data Width Reduction, and Round Unrolling on area, and power consumption. These are tested on three lightweight ciphers: LiCi, ANUII, and QTL. Data Width Reduction reduces area by using only a fraction of the original datapath. It was however found to be ineffective for the chosen ciphers, increasing area by 5.64%, 6%, and 9.2% in LiCi, ANUII, and QTL, respectively. Round Unrolling reduces latency which lessens the contribution of static power for each computation. Results show that round unrolling improves power efficiency by 25.97%, 3%, and 14% in LiCi, ANUII, and QTL, respectively. This comes at 299%, 414%, and 52% increase in area. The results allow newer and better lightweight ciphers to be further improved for small scale devices.

Achieving 100 Gbps+ throughput with commodity servers is a challenging goal, even with state-of-the-art Data Plane Development Kit (DPDK). Fundamental performance of CPU/Memory is now the bottleneck and simple code optimization of Network Functions (NFs) cannot be the solution. Hardware accelerators including FPGA are getting attentions for performance boost; however, relying on specific features degrades manageability of NFV-nodes. Common Receive Side Scaling (RSS) provides a means of H/W-level parallelization, but per-flow throughput is not accelerated. Existing software-based approaches distribute processing load of NFs, but I/O is still serialized for each datapath. We tackled I/O parallelization and uncovered encounterd certainly misty contentions in our previous study. Specifically, per-thread CPU cycle consumptions proportionally grew as increasing parallelization level, although the overhead of conceivable mutual executions (e.g. CAS operations) was trivial. In this paper, we pursue the cause of the issue and upgrade our I/O parallelization scheme. Our careful investigation of NFV-node internals ranging from application to device driver layers indicates that hidden H/W-level contentions involving DMA heavily consume CPU cycles. We propose a contention avoidance design of thread role assignment and prove our design can flatten per-thread CPU cycle consumptions.

In this paper, a 32-bit Datapath with RISC-V instruction set architecture based on RV32I CPU instruction set has been designed. Furthermore, through analysis of function and theory of RISC-V CPU instruction set, the processor has been optimized by designing a six staged folded pipeline core. Finally, the design has been examined on the current industrial standards FPGA boards. Synthesis and implementation on two Boards of Virtex family has been compared on the basis of Utilization reports and Power Reports. The comparison shows the more heavily configurable board i.e. the Virtex Ultrascale delivers better power – performance tradeoff at higher costs.

Convolutional Neural Networks (CNNs) for Artificial Intelligence (AI) algorithms have been widely used in many applications especially for image recognition. However, the growth in CNN-based image recognition applications raised challenge in executing millions of Multiply and Accumulate (MAC) operations in the state-of-the-art CNNs. Therefore, GPUs, FPGAs, and ASICs are the feasible solutions for balancing processing speed and power consumption. In this paper, we propose an efficient hardware architecture for CNN that provides high speed, low power, and small area targeting ASIC implementation of CNN accelerator. To realize low cost inference accelerator. we introduce approximate arithmetic operators for MAC operators, which comprise the key datapath components of CNNs. The proposed accelerator architecture exploits parallel memory access, and N-way high speed and approximate MAC units in the convolutional layer as well as the fully connected layers. Since CNNs are tolerant to small error due to the nature of convolutional filters, the approximate arithmetic operations incur little or no noticeable loss in the accuracy of the CNN, which we demonstrate in our test results. For the approximate MAC unit, we use Dynamic Range Unbiased Multiplier (DRUM) approximate multiplier and Approximate Adder with OR operations on LSBs (AOL) which can substantially reduce the chip area and power consumption. The configuration of the approximate MAC units within each layer affects the overall accuracy of the CNN. We implemented various configurations of approximate MAC on an FPGA, and evaluated the accuracy using an extended MNIST dataset. Our implementation and evaluation with selected approximate MACs demonstrate that the proposed CNN Accelerator reduces the area of CNN by 15% at the cost of a small accuracy loss of only 0.982% compared to the reference CNN.

This paper presents a compact architecture of CNN training accelerator targeted for mobile devices. Accuracy was verified using python in the CNN structure, and accuracy was compared by applying several data types to find optimized data types. In addition, floating-point operations are used in the computation of the CNN structure, and to implemented them, we have created and verified the addition, subtraction, and multiplication circuits of floating-point. The CNN architecture was verified using python, the floating point operation was verified using Vivado, and Area was verified TSMC 180nm.

We present an approach to teach RISC processor design for an undergraduate computer architecture course specifically aimed to reduce the gap between a high-level datapath block diagram and a complete Verilog code specification. We propose a graphical approach designed to develop an understanding of the MIPS processor organization at the Verilog structural level by using an online browser-based simulator, from a single cycle design to pipeline design. The students are lead through a series of examples, step by step, and they can actively be involved in the processor design process. We believe that the best choice should not introduce excessive complexity that becomes a barrier in describing the interconnection of a high-level diagram and the Verilog implementation code.

This paper describes an energy-security scalable crypto-core for private-key cryptography in low-end sensor nodes based on SIMON cipher. Energy and area footprints are reduced through techniques at the algorithm, microarchitectural and gate level. At the algorithm level, multiple encryption is introduced to dynamically expand the key length from 64 to 256 bits at minimal reconfiguration complexity, allowing shorter keys and lower energy when lower level of security is demanded. The 1-round parallel architecture with short 32-bit datapath narrows the traditionally large gap between the conventional crypto-core data (e.g., 128 bits) and low-end processors (32 bit or lower), mitigating or eliminating the need for area- and energy-hungry FIFO buffers at their interface. At the gate level, the adoption of multi-bit pulsed latch-based pipelines with internal clock buffer sharing reduces the dominant clock power/area contribution of sequential elements. Tunable clock duty cycle allows time borrowing for improved variation resilience at ultra-low voltages at low hold-fix buffer count, leveraging the inherent margin against hold time violations enabled by relatively uniform pipestage delays. A 40 nm testchip shows energy down to 0.31 pJ/bit at 0.45 V with 64-bit key and 0.79E6 F2 area (F = process minimum feature size). The proposed crypto-core is well suited for ubiquitous security in energy/area-constrained platforms (e.g., low-end sensor nodes, RFIDs), while preserving full 256-bit security when necessary.

This paper presents a low-complexity parallel multiuser detector architecture for interleave division multiple access systems. To facilitate efficient hardware implementation, the formulae associated with the elementary signal estimator (ESE) are reorganized. Grounded on the reorganization, the proposed ESE circumvents redundant computations, and takes advantage of carry-save additions. The resulting datapath is further simplified by approximations that do not deteriorate the error rate noticeably. Prior to integrating with such ESEs, the state-of-the-art parallel architecture for the user-specific processing block (UPB) is also simplified by rescheduling the memory-access pattern. As a result, a prototype 2-parallel 16-user detector that incorporates the proposed ESEs and UPBs in a 65-nm CMOS occupies 23% less silicon area, dissipates 21% less power, and takes 50% less latency than the state-of-the-art serial detector.

We propose Critical Datapath Length (CDL), a powerful, interpretable metric of neural-network models that enables accurate execution time prediction on parallel device architectures. CDL addresses the fact that the total number of floating-point operations (FLOPs) in a model is an inconsistent predictor of real execution time due to the highly parallel nature of tensor operations and hardware accelerators. Our results show that, on GPUs, CDL correlates to execution time significantly better than FLOPs, making it a useful performance predictor.

This paper presents a novel high speed implementation of Andrew's Convex Hull Monotone Chain software algorithm on FPGA. Convex hull in its simplest form is the smallest convex polygon that contains a set of discrete points with many applications in engineering, mathematics and science. Convex hull algorithm in its best case has a linear time complexity assuming data points are sorted. Our implementation targets Zynq system on chip platform. We accelerate the software algorithm by designing components that can work in parallel. This involves using burst transfer, dynamic branch prediction, and resource sharing.. Our approach achieves a speed up of 2.18 for 4 levels of parallelism at 100 MHz clock. Higher speed up can be attained by increasing the levels of parallelism. To the best of our knowledge, our proposed method is the only available hardware accelerated implementation that truly optimizes the hull processing datapath. This is in contrast with other competitive software acceleration which reduce the number of data points to be processed using additional preprocessing steps or increase the speedup by using high speed interface.

The protection of the Intellectual Property (IP) has emerged as one of the most serious areas of concerns in the semiconductor industry. Logic locking has shown to lead to good results, with little overhead against Integrated Circuit (IC) over-production and IP piracy by untrusted end-users or foundry. Unfortunately new attack techniques appear each time a new locking mechanisms is presented to exploit its weakness. Some include path sensitization and more recently SAT-based attacks. This work proposes a functional locking mechanisms for behavioral IPs (BIPs) that exploits the internal structure of behavioral descriptions when synthesized with High-Level Synthesis (HLS). In particular the generation of a Finite State Machine (FSM) and a datapath. Our proposed locking mechanism increases the key size by breaking it into multiple pieces, each applied at a unique FSM state. Applying the incorrect key at any of the states leads to an invalid results. Breaking our proposed locking mechanism is much harder than previous work as the attacker would need to try all possible permutations of keys to find the correct key, thus making this virtually unbreakable. Moreover, we insert the key at the BIP itself, which implies that the locking logic is shared with the BIP logic, hence making it more robust against removal attacks. Experimental results show that the proposed locking mechanism works very well with minimal area and delay overheads for different key sizes.

Lattice-based cryptography has been growing in demand due to their quantum attack resiliency. Polynomial multiplication is a major computational bottleneck of lattice cryptosystems. To address the challenge, lattice-based cryptosystems use the Number Theoretic Transform (NTT). Although NTT reduces complexity, it is still a well-known computational bottleneck. At the same time, NTT arithmetic needs vary for different algorithms, motivating flexible solutions. Although there are prior hardware and software NTT designs, they do not simultaneously offer flexibility and efficiency. This work provides an efficient and flexible NTT solution through domain-specific architectural support on RISC-V. Rather than using instruction-set extensions with compiler modifications or loosely coupling a RISC-V core with an NTT co-processor, our proposal uses application-specific dynamic instruction scheduling, memory dependence prediction, and datapath optimizations. This allows achieving a direct translation of C code to optimized NTT executions. We demonstrate the flexibility of our approach by implementing the NTT used in several lattice-based cryptography protocols: NewHope, qTESLA, CRYSTALS-Kyber, CRYSTALS-Dilithium, and Falcon. The results on the FPGA technology show that the proposed design is respectively 6x, 40x, and 3x more efficient than the baseline solution, Berkeley Out-of-Order Machine, and a prior HW/SW co-design, while providing the needed flexibility.

A robust design, which is one of the main requirements for space applications is always a tradeoff between power and area budget, speed requirement and the overall reliability. The occurrence of Single Event Effects (SEE) induced by energetic particle hits in the silicon leads to the insertion of additional replica logic at the design phase in order to tolerate Single Event Upsets (SEU) or Single Event Transients (SET). One of the most traditional circuit design technique is Triple Modular Redundancy (TMR). This paper presents a design concept for Radiation-Hardness-by-Design (RHBD) of TMR standard cell gates with local SET filter on the datapath, composed of True Single-Phase Clock (TSPC) flip-flops. The circuit architecture of the novel TSPC$- \Delta$ TMR flip-flops is discussed and compared to the baseline standard cell D-flip-flop. Analog simulations under various process, voltage, and temperature (PVT) conditions show an improvement by 50% of the gate delay of the baseline TSPC flip-flop. Moreover, the proposed TSPC$- \Delta$ TMR gate candidate has a delay overhead of only 130ps under worst case condition compared to the classical unhardened D-latch-based reference flip-flop. Test vehicles for electrical measurements and radiation tests are implemented in $0.13 \mu \mathrm{m}$ BiCMOS technology.

This letter presents a novel timing error detection and correction (EDaC) technique to reduce design margins in a near/sub-threshold RISCV-IM32 microprocessor. The proposed technique takes a snapshot of the datapath’s activity just before the launch of the next clock to determine if a timing error will occur. If so, it prevents the error at the last moment by gating the clock with one cycle. This avoids imposing additional hold constraints on the design and removes the need for a complex correction mechanism. The design is implemented in FDSOI 28 nm and achieves a margined minimum energy point (MEP) of 1.32 pJ/cycle at 3 MHz and 0.434 V. The EDaC technique robustly eliminates all voltage margin, resulting in an improved MEP of 0.92 pJ/cycle and 0.345 V at the same frequency. ispartof: IEEE Solid-State Circuits Letters vol:3 pages:230-233 status: published

Speech segments are broadly categorized as voiced (V), unvoiced (UV), and silence (S). The V/UV/S classification of speech segments plays an important role in many speech-based applications. In this paper, we propose a digital architecture for instantaneous V/UV/S classification of noise free speech segments. The proposed architecture uses the incoming samples of the speech segments to compute two popularly used time-domain-based speech parameters namely short-time energy (STE) and short-time average zero-crossing rate (STAZCR). These computed parameters are used along with pre-determined STE and STAZCR thresholds by the decision logic to classify the speech segments. The necessary hardware to perform on-the fly computations of the said parameters is realized using an algorithmic state-machine with datapath (ASMD). The decision logic is realized as a standalone unit, integrated with the ASMD. Further, the proposed architecture can be reconfigured to work with speech segments having variable lengths in powers of 2, upto 1024. The proposed architecture is prototyped on field-programmable gate array (FPGA) using Xilinx Zedboard Zynq Evaluation and Development Kit XC7Z020CLG484-1. The implementation results show that the proposed architecture utilizes minimal resources on FPGA fabric, and achieves maximum operating clock frequencies up to 185 MHz.

Resource balancing has been effectively used to mitigate the long-term aging effects of Negative Bias Temperature Instability (NBTI) in multi-core and Graphics Processing Unit (GPU) architectures. In this work, we investigate this strategy in Coarse-Grained Reconfigurable Arrays (CGRAs) with a novel application-to-CGRA allocation approach. By introducing important extensions to the reconfiguration logic and the datapath, we enable the dynamic movement of configurations throughout the fabric and allow overutilized Functional Units (FUs) to recover from stress-induced NBTI aging. Implementing the approach in a resource-constrained state-of-the-art CGRA reveals $2.2\times$ lifetime improvement with negligible performance overheads and less than $10\%$ increase in area., Please cite this as: M. Brandalero, B. N. Lignati, A. Carlos Schneider Beck, M. Shafique and M. H\"ubner, "Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation," 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2020, pp. 1-6, doi: 10.1109/DAC18072.2020.9218586

Intel’s Nervana Neural Network Processor for Training (NNP-T) contains at its core an advanced floating point dot product design to accelerate the matrix multiplication operations found in many AI applications. Each Matrix Processing Unit (MPU) on the Intel NNP-T can process a 32x32 BFloat16 matrix multiplication every 32 cycles, accumulating the result in single precision (FP32). To reduce hardware costs, the MPU uses a fused many-term floating point dot product design with block alignment of the many input terms during addition, resulting in a unique datapath with several interesting design trade-offs. In this paper, we describe the details of the MPU pipeline, discuss the trade-offs made in the design, and present information on the accuracy of the computation as compared to traditional FMA implementations.

Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor performance and usability. This paper proposes a high-level synthesis framework of OpenCL for FPGAs, called SOFF. It automatically synthesizes a datapath to execute many OpenCL kernel threads in a pipelined manner. It also synthesizes an efficient memory subsystem for the datapath based on the characteristics of OpenCL kernels. Unlike previous high-level synthesis techniques, we propose a formal way to handle variable latency instructions, complex control flows, OpenCL barriers, and atomic operations that appear in real-world OpenCL kernels. SOFF is the first OpenCL framework that correctly compiles and executes all applications in the SPEC ACCEL benchmark suite except three applications that require more FPGA resources than are available. In addition, SOFF achieves the speedup of 1.33 over Intel FPGA SDK for OpenCL without any explicit user annotation or source code modification.