33 results on '"Damiani M"'
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2. Boolean function representation using parallel-access diagrams.
3. Synthesis of self-testing finite state machines from high-level specification.
4. Nondeterministic finite-state machines and sequential don't cares.
5. Scheduling with environmental constraints based on automata representations.
6. Synthesis and optimization of synchronous logic circuits from recurrence equations.
7. An advanced information management system.
8. Improved testability evaluations in combinational logic networks.
9. Aliasing errors in signature analysis testing of integrated circuits.
10. Synthesis of combinational circuits with special fault-handling capabilities.
11. Reliability evaluation of combinational logic circuits by symbolic simulation.
12. Aliasing minimization in signature analysis testing.
13. Observability don't care sets and Boolean relations.
14. Aliasing in signature analysis testing with multiple-input shift-registers.
15. Estimate of signal probability in combinational logic networks.
16. Boolean function representation based on disjoint-support decompositions.
17. Recurrence equations and the optimization of synchronous logic circuits.
18. Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters.
19. Novel design for testability schemes for CMOS ICs.
20. Scheduling and control generation with environmental constraints based on automata representations.
21. Optimization of combinational logic circuits based on compatible gates.
22. Don't care set specifications in combinational and synchronous logic circuits.
23. Testability measures in pseudorandom testing.
24. Fault simulation of unconventional faults in CMOS circuits.
25. Aliasing in signature analysis testing with multiple input shift registers.
26. An analytical model for the aliasing probability in signature analysis testing.
27. Analysis and design of linear finite state machines for signature analysis testing.
28. Synchronous logic synthesis: circuit specifications and optimization algorithms
29. On the design of multiple-input shift-registers for signature analysis testing.
30. CMOS design for improved IC testability.
31. A synthesis framework based on trace and automata theory.
32. Synthesis of multilevel fault-tolerant combinational circuits.
33. Synchronous logic synthesis: circuit specifications and optimization algorithms.
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