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A power-reconfigurable distributed amplifier (DA) is implemented using a 130 nm metamorphic high-electron mobility transistor (mHEMT) process. Using a mHEMT process with excellent high-frequency characteristics, output power and efficiency at high frequencies are improved compared with the existing power-reconfigurable distributed amplifiers. In this article, a gain cell switching technique is proposed as the power reconfiguration method for the distributed amplifier. The gain cell switching technique expands the gain bandwidth and power reconfigurability more than the conventional bias control. The proposed power-reconfigurable DA obtains a measured linear gain of 10.0–13.6 dB from 0.5 to 62.5 GHz and a measured output power of 20.2–21.5 dBm from 10 to 40 GHz. A measured power added efficiency (PAE) is 11.6–20.0% from 10 to 40 GHz. Under a low power mode (LPM), it obtains a measured linear gain of 4.4–7.1 dB from 0.5 to 65 GHz and a measured output power of 14.7–15.9 dBm from 10 to 40 GHz. At 10 GHz, a drain efficiency (DE) is 11.4% at 5.6 dB power back-off. This is 6.5% higher than the conventional DA or more than twice as high.

One of the key challenges in the practical realization of industrial internet of things (IoT) is overcoming Faraday shielding of free space electromagnetic waves emanating from the antennas of wireless systems used for power and data transfer. Metallic structures, machinery, pipeline, etc., cause interference resulting in the loss of signal connectivity among sensor network. Currently available techniques based on ultrasonic-electromagnetic transducers pose severe limitations on frequency, efficiency, and alignment. Here we demonstrate exciting Zenneck type interface waves propagating as localized charge oscillations (modes) along the metal profile, which overcomes the restrictions on frequency, metal obstacles, partial enclosures, and alignment. A finite element methods (FEM) model developed to predict the signal reception and power transfer efficiency across metal infrastructure shows excellent agreement with the experimental results. Electrical power transfer using Zenneck, under open conditions, show 4% drop for distance of 1 to 8 meters (68 to 64%), and 9% drop under shielded conditions for the same range (66 to 57%). For data transmission results, we demonstrate a feasibility, for an input power of 0dBm with several metallic pipelines as obstacles show received power of −11.8 dBm and −19.01 dBm at 6 and 25 meters, respectively.

In this paper, a simplified soft-output direct detection faster than Nyquist (SO-DD-FTN) algorithm is proposed to eliminate severe inter-symbol interference in optical interconnects. The feasibility of the proposed algorithm is verified in a C-band 56-Gb/s 4-ary pulse amplitude modulation (PAM-4) system using 10G-class optics, and the 3-dB system bandwidth is only 5.5 GHz. Compared to conventional SO-DD-FTN, the simplified SO-DD-FTN not only reduces 90% multiplication complexity and 80% addition complexity, but also has almost no performance degradation. Experimental results show that, for the back-to-back case, the achieved receiver sensitivity using simplified SO-DD-FTN has 4.5-dB improvement compared with conventional direct detection faster than Nyquist (DD-FTN). As for 20-km standard single-mode fiber (SSMF) transmission application, since the system suffers from both optical/electronic bandwidth limitation and dispersion-induced power fading, the conventional DD-FTN cannot achieve the bit error rate (BER) threshold of 10-3, while the simplified SO-DD-FTN can achieve the BER threshold at received optical power of -14.5 dBm. In conclusion, the proposed simplified SO-DD-FTN algorithm achieves superior performance with low computational complexity and has the potential for applying to optical interconnects.

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

In this paper, in-band continuous mode transferring (CMT) method is presented for designing broadband Doherty power amplifier (DPA). Specifically, transferable continuous mode, transferring between class-J continuum to class-F-1 continuum, is introduced into DPA at output back-off (OBO) power level for improving bandwidth and efficiency. For validation, a broadband DPA with operation mode transferring from continuous class-J to continuous class-F-1 is designed, fabricated and measured. Experimental results show the drain efficiencies (DEs) of the fabricated DPA are 46.3%-57.7% and 58.4%-69.1% at 6 dB OBO and peaking power levels over 1.7-2.6 GHz. The saturation power of this DPA is 43.1-45.2 dBm with a gain of 9.1-11.2 dB in the interested band. Furthermore, when the fabricated DPA is stimulated by a 20 MHz wideband signal with a peak-to-average power ratio (PAPR) of 7.05 dB at 2.4 GHz, the measured average power is 36.5 dBm with an average DE of 45.7%, and the measured adjacent channel leakage ratios (ACLRs) are -31.9 dBc and -50.4 dBc before and after DPD technique, respectively.

We demonstrate high saturation output power under high temperature (75°C) by using active-MMI SOA on quantum dot. Significant enhancement of 15 dBm saturation output power was confirmed successfully.

An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. The current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0 dBm, and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.

This paper presents a 30-to-40 GHz 2-stage power amplifier (PA) for 5G applications. Transformers are used to achieve a broad input, output and interstage matching while occupying a compact size. The neutralization technique is used to boost the power gain and improve stability of PA. According to the simulation results, the power amplifier achieves an output 1dB compression point (OP1dB) of 14.9 dBm and a saturated output power of 17.4 dBm with a peak power added efficiency (PAE) of 39% at 35 GHz. The gain is larger than 30 dB from 30–40 GHz. Implemented in a 0.13-µm SiGe BiCMOS process, the overall chip size is 0.46 mm2 including all RF and DC pads.

This paper presents a 53.25 GHz to 213 GHz frequency quadrupler with an output bandwidth of 15.5 GHz. In saturation the system achieves 11.8 dB of conversion gain at 2 dBm of saturated output power. Consuming 92.9 mW of DC power, the power-added efficiency is 1.6 %, a 28.7 % against the current state of the art. Harmonic suppression greater than 30 dB over the full 3-dB-bandwidth is achieved, while the rejection at center frequency is greater than 45 dB. Being the first in its class to combine large power delivery with high conversion gain, more than doubling the state of the art, the demonstrated quadrupler qualifies for application in large-scale transceivers where high levels of local oscillator signal powers need to drive several parallel de-/ modulator stages.

The duplexer is a key device for simultaneous signal transmission and reception, and a lot of duplexers based on frequency division principle have been proposed. However, there are some defects of duplexers based on frequency division such as interference between the transmitting and the receiving signals. Development of dual-polarization transmit and receive module offers a significant way to solve the above problems. However, limited by the processing accuracy and other issues, there are very few orthomode polarization duplexers designed for the terahertz frequency band. In this article, a novel duplexer in THz band is proposed. The structure of the duplexer proposed in this paper is very simple, easy to process in the terahertz frequency band, and has very good realizability. The simulation results of the duplexer show that the insertion loss of both two modes is less than 0.2 dBm, the return loss is better than 20 dBm, and the isolation of two orthomodes is better than 68 dBm.

In this paper, a dual-band power amplifier (PA) fabricated in 0.15-μm GaAs pHEMT process is presented. The concept of the optimal matching contour is used in the matching network design to minimize the loss in both operating frequency bands. Thus, this PA achieves good power performance in both frequency bands. The measured results of small-signal gain are 20/12 dB at 28/39 GHz, respectively. The saturated output power (P sat ) is 21.9/22.7 dBm, the peak power-added efficiency (PAE max ) is 28.9/32.6%, and the OP 1dB and corresponding PAE (PAE 1dB ) are 21.8/22.6 dBm and 28/32% at 28/39 GHz, respectively.

We designed C+L band light sources with Bi/Er/La co-doped silica fibers. The broadband one had fluorescence intensity of −21.00 dBm in 1527–1612 nm, and the different-wavelength lasers were generated.

This paper introduces a Ka-band power amplifier with 14.2-dBm Power. Multiple transformer-based matching networks are introduced to realize broadband matching and high power output. A 26–35GHz power amplifier is realized in a standard 65 nm CMOS process. The amplifier achieves 16.8 dB small signal gain, 14.2-dBm output 3-dB compression point (P3dB), and 11.8-dBm output 1-dB compression point (P1dB). The simulated input and output return losses within the operation band are −6dB and −9dB in the worst case, respectively.

This study demonstrates the protection effects using transient voltage suppressor (TVS) diodes-based circuits under high power microwave (HPM) pulses. Two types of TVS diodes were studied, and their dynamic resistances versus the input power were obtained. Five types of topology using these two TVS diodes-based circuits were designed and compared with their voltage-ampere characteristics. The dynamic resistances of each branch of two typical circuits were simulated and compared. These TVS diodes-based protection circuits were measured under HPM pulses with their protection effects recorded. The highest protection ratio of these circuits is approximately 17 to 20 dB when the input power of HPM pulses ranges from 50 to 62.5 dBm. The simulated and measured results show close correlations. This analysis is useful for further electromagnetic protections under HPM pulses.

A 28-GHz power amplifier (PA) with adaptive cross feedback (ACF) is presented. The ACF is employed by an adaptively controllable RC-feedback circuit from the source to the opposite drain nodes of the common-gate (CG) stages in a differential cascode amplifier. The proposed ACF makes the PA stable even with large power transistors. It also linearizes the PA by decreasing the feedback adaptively at high powers which improves amplitude distortion (AM-AM) and power-added efficiency (PAE) as well as the saturation power (P Sat ). The proposed PA is implemented with a 28-nm bulk CMOS process with a 0.144 um2core chip area. It is shown that the ACF increases P Sat , peak PAE, and output 1-dB gain compression point (OP 1dB ) from 20.1 dBm to 20.4 dBm, 34% to 37.2%, and 17.4 dBm to 18.2 dBm, respectively at 28.5 GHz. The proposed PA shows a 28-dB peak gain at 28.6 GHz with 26.8 GHz to 30.8 GHz (14.0%) 3-dB gain bandwidth, which is the highest P Sat and gain among the reported Ka-band bulk CMOS PAs.

We present the design and measured performance of a two-stage ~ 2.3 GHz diode-based parametric frequency selective limiter (pFSLs), built on a FR-4 printed-circuit-board (PCB) and showing record-low power threshold ( $P_{th}$ , equal to −10.8 dBm) and insertion-loss value (ILS.S, equal to 1.66 dB) for driving power levels (P in ) lower than P th . Thanks to its optimally engineered dynamics, the built pFSL can not only selectively attenuate undesired signals with power levels ranging from −10.8 dBm to 4 dBm, but it also provides a strong suppression level (IS> 19 dB) when driven by much higher P in values than P th , even approaching 28 dBm. The record performance demonstrated in this work proves, for the first time, that diode-based pFSLs are suitable to increase the resilience to electromagnetic interference (EMI) even of those wireless radios designed for low-power consumption and, consequently, characterized by a narrow dynamic range.

This paper presents a 39 GHz front-end module (FEM) in 22 nm FD-SOI technology for 5G communications. The PA output stage uses a 2-stacked FET topology to achieve high output power. A two-way current combiner is used to combine output power from the output stage while maintaining a uniform waveform distribution over each transistor unit cell to enhance the device reliability. The LNA consists of two stages to obtain high power gain with low power consumption. Derivative-superposition (DS) with a common-mode inductor is used to improve the LNA linearity. The measured P sat and PAE max in TX mode are 20.4 dBm and 25.6%, respectively. The measured NF and IIP3 in RX mode are 5.7 dB and −13 dBm, respectively. A Pout, avg of 13.5 dBm and a PAE avg of 10.6% is achieved in 64-QAM 400 MSym/s single-carrier at EVM rms of −25 dB for TX-mode.

In this paper, new parallel plate coupler based Doherty power amplifier design for 5G NR handset applications is proposed. Based on simplified output network, the proposed Doherty power amplifier is analyzed. The proposed Doherty power amplifier is demonstrated experimentally with GaAs-HBT. A PAE of 42.0% and a NR ACLR of −38.8 dBc at an average output power of 27.8 dBm are measured at 3.75 GHz under 5G NR 100 MHz, DFT-s-OFDM, QPSK operation, and the efficiency improvement from Class AB operation achieves 11%. Moreover, the proposed Doherty power amplifier maintains more than 35.0% efficiency with a NR ACLR of below −35.2 dBc from 3.35 GHz to 4.15 GHz, corresponding to 5G NR Band n77.

This paper presents a switchless bidirectional power amplifier-low noise amplifier (PA-LNA) in 90-nm CMOS process for millimeter-wave (mm-wave) phased-array front-end chip. This PA-LNA uses current-type transformer (TF) as a bidirectional matching network for PA and LNA inputs/outputs without using lossy T/R switches. As a side benefit, avoiding the use of the T/R switches not only saves the chip area, but also prevents performance degradation in PA and LNA modes. The proposed PA-LNA achieves peak small-signal gain of 18.3 dB and 17.6 dB in PA and LNA mode, respectively. In the PA mode, it achieves the measured peak saturated output power (Psat) of 15.1 dBm with 29 % peak power-added efficiency (PAE MAX ) and 13.3 dBm peak 1-dB output power (OP 1dB ) at 33 GHz, while LNA mode achieves minimum noise figure (NF) of 4.7 dB at 36 GHz. The reverse isolation in both modes is better than 43 dB. The core size without pads is 0.21 mm2.

This paper presents a D-band linear power amplifier (PA) with high gain, high output power and high efficiency using CMOS 45nm RFSOI process. An 8-way (4-way differential) power-combining technique is implemented to increase the power amplifier linearity and output power. To decrease the loss of the output combiner, the first stage output power combiner is designed as part of the power matching network. The PA achieves a small-signal gain of 22.2-24 dB with 1-1.2 V supply at 140 GHz, respectively. The measured P1dB and Psat are 14.2 dBm and 17.5 dBm with 1.2 V supply, at 140 GHz. The maximum PAE is 13.4%. The 140 GHz PA operates from 130 to 150 GHz with an OP1dB > 13 dBm, which is ideal for high-speed wireless communication systems.

A low-loss compact-size edge-coupled 4-way balun that simultaneously converts a single-ended signal to two pairs of differential signals is proposed. A 2-way combined differential power amplifier (PA) operating at 60 GHz is designed with the proposed 4-way balun in 0.18 µm SiGe technology. It consists of two identical 3-stage differential unit PA cells, which is internally transformer-coupled and capacitive-neutralized. The designed PA achieves a small signal 3-dB bandwidth from 43 to 67 GHz, with a peak gain of 20 dB. The 1 dB power compression point (P1dB) is 21.6 dBm and saturated output power (P SAT ) is 22.7 dBm, with power added efficiency of 23.5% at PldB and 27.7% at PSAT. The modulation test shows that the PA can deliver 18.1 / 15.2 dBm average output power with −14.5 / −21.8 dB error-vector magnitude when operating with IEEE 802.11ad modulation coding schemes (MCS) 9 / IEEE 802.11ad MCS 12 signals.

This paper presents optimal carrier and peaking drain voltages to preserve the output power capability and back-off level of Doherty power amplifiers (PAs) operating for non-optimal loads. These voltages are theoretically obtained from back-off and full power conditions. A performance comparison between simulations of a conventional Doherty and the proposed load insensitive version is presented, showing that the introduced theory can be very advantageous for operation under load varying scenarios. A 3.6 GHz load insensitive Doherty PA was designed, implemented and measured for loads distributed inside a 2.0 voltage standing wave ratio circle. These measurements validated the introduced theory, showing an almost constant maximum output power (42.9 – 43.2 dBm), and a back-off level varying between 5.0 dB and 6.2 dB. The 6-dB output power back-off efficiency varies between 42 % and 53 %, in which the highest degradation corresponds to loads with high imaginary parts.

In this paper, we present a GaN-based f T -doubler topology using a novel integrated layout. This compact approach allows for minimizing the layout-induced parasitic effects and, as a result, enables operation at millimeter-wave frequencies. In order to demonstrate the broadband potential of the f T -doubler topology employing the novel integrated layout approach, a 3-stage amplifier is reported. It can provide more than 10 dB of small-signal gain over a 28-90-GHz band, which is equivalent to a fractional operating bandwidth of 105 % (1.68 octaves). In large-signal operation, this MMIC can deliver from 14.5 dBm to 20.6 dBm of output power over a 30-90-GHz band. This circuit is able to provide a full coverage of the Q-band (33–50 GHz), U-band (40–60 GHz), V-band (50–75 GHz), E-band (60–90 GHz), and almost the entire Ka-band (26.5-40 GHz). To the best of our knowledge, this is the first demonstration of an FET-based integrated f T -doubler circuit operating at such high frequencies.

Access to reliable and accurate bathymetric data is fundamental to many marine activities. This paper proposes a merge-normalization (MN) method that is suitable for multisource bathymetric data fusion in deep ocean areas, to solve the problem of difficult to integrate high-precision digital bathymetric model (DBM) for complex sources and various resolutions of global deep ocean bathymetric data. Then we apply it to the DBM construction of the Mariana Trench. The method combines multibeam, single-beam, and electronic navigational chart data with Shuttle Radar Topography Mission (SRTM) dataset by using the workflow of merging and normalizing, which can fill the data gaps while preserving topographic details in high-resolution bathymetric data. Compared with the widely used General Bathymetric Chart of the Oceans (GEBCO) dataset, the Mariana Trench dataset constructed in this study demonstrated improved accuracy, resolution, and topographic detail, highlighting the value of the application of the method and of its development potential.

A compact rectifier with high efficiency at wide input power dynamic range is proposed in this paper. The circuit consists of a matching network, two shunt connected diodes with an integrated impedance compression network (IICN) and a dc-pass filter. The IICN significantly reduces the diode impedance variation when input power changes, hence improves matching as well as efficiency of the rectifier at wide input power dynamic range. Different from the conventional resistance/impedance compression networks, which can only work under certain impedance condition with dual-branch topology, the IICN can directly operate two diodes in parallel in a single-branch with no impedance limitation. Thus, less components and branch are needed, resulting in size reduction and lower circuit complexity. The design flexibility is also enhanced. Mechanism of the IICN is analyzed. A prototype operating at 2.45 GHz is optimized, fabricated and measured. The total size of the prototype is 0.18λ2. The efficiency higher than 70% of the peak value is realized at input power ranging from 0.8 dBm to 18.0 dBm.

In this paper, a multi-mode magnetically coupled and tuned inductive peaking technique with impedance transforming capability is proposed to achieve a wider operational locking range in the injection locked frequency divider (ILFD) for low injected power levels. Fabricated in 65 nm CMOS process, the proposed ILFD operating at 60 GHz, achieves a locking range of 16.3% from 53.2 to 63 GHz with a low injected power of -10 dBm. Occupying a small area of 0.0288 mm2, the ILFD delivers an average single-ended output power of -6 dBm with a dc power consumption of 3.7 mW from a 1.2 V supply voltage. The power efficiency (Pout/Pdc) of the proposed ILFD is 6.8%.

This paper presents a 30 MHz-2.7 GHz broadband high-gain power amplifier (PA) in 0.25 µm GaAs PHEMT technology. The fabricated two-stage PA obtains a small signal gain higher than 35.0 dB and saturated output power of 37.2±1.6 dBm from 30 MHz to 2.7 GHz, with a peak power added efficiency (PAE) of 46.2% at 500 MHz. To our knowledge, this is the first report to achieve the highest gain and output power in broadband GaAs amplifier below 2.7 GHz.

Two monolithic microwave integrated circuit (MMIC) power amplifiers (PAs) using 0.1 um GaN process are presented in this work. The PAs are designed to work from 24 to 30 GHz, covering the frequencies like 24.25-27.5 GHz, 27.5-28.35 GHz and 27.5-29.1 GHz for 5G millimeter-wave (mm-Wave) bands. A harmonic-controlled output matching method is used to improve bandwidth and efficiency for two PAs, one is a single stage PA and the other is a two-stage two-way combined PA. The single stage PA has a first measurement results of 25 dBm output power and 25% power-added efficiency (PAE), which are 3.5 dB and 11 % lower than the simulation results. The total sizes of the chips are 1.05*0.65 mm2 and 1.75*1.25 mm2, respectively. The single stage PA is packaged and the measured results agree with the simulated results in terms of small signal performance.

This paper presents a 62 GHz, mixed-mode compact Doherty Power Amplifier (DPA) with high linearity and efficiency implemented in a 65-nm CMOS technology. The DPA adopts a novel linearity boosting and efficiency enhancement technique by introducing a dynamic-power-allocation mechanism which is realized by a coupler-based power divider and a mixed-mode DPA architecture. By adjusting the control voltages of the PA in the gain stage, the input power allocated to both paths change, leading to a measured $OP_{1dB}$ increase from 11.72 dBm to 14.2 dBm, a maximum 15.6 dBm output power and a 9.09% PAE improvement at the 1-dB compression point. A novel compact three-coil-coupled transformer along with an output matching capacitor are proposed as the power combiner, output matching network, balun, and impedance inverter. The core part of the fabricated DPA occupies an area of 0.04 mm2, exhibits a 15.6 dBm saturated output power, a peak power gain of 19 dB, an OP 1dB of 14.2 dBm, with a 28.9% peak power-added efficiency (PAE), and a 27.2% PAE at 1-dB compression point, and a 12.7% PAE at 6-dB back-off. The DC power consumption of the PA is only 68 mW.

In this work, the design of a wideband millimetre-wave (mm-Wave) power amplifier (PA) is presented. To ensure the designed PA has not only a sufficient output power with good power-added efficiency (PAE) but also superior input and output impedance matching, a balanced amplifier (BA) architecture is used. A prototype PA is designed in a 0.13-µm SiGe HBT technology. With a 1.6- V power supply, the PA can deliver more than 15 dBm saturated output power between 85–100 GHz that is equivalent to more than 16% fractional bandwidth. The peak PAE is better than 14.7% within this frequency range. The overall physical dimension of the designed PA is very compact. Including all pads, it is only 0.6 mm x 0.9 mm.

In this paper, a broadband high-efficiency power amplifier (PA) with a Class-J mode matching network is proposed. The output power can be improved by employing a stacked structure, additionally, the Class-J theory provides a superior method to broaden the operating frequency range among X-band with high efficiency. And the output matching network is simplified especially, exploiting the wideband nature of continuous mode Class-J PA. The circuit is fabricated in a 130 nm standard CMOS process. The power added efficiency (PAE) is greater than 20% over the range of 8.1~11.1 GHz and reaches the maximum value of 29.7%, the power gain reaches more than 12 dB over this frequency range. The saturated output power is 20.2 dBm when the input power is 5 dBm.

A source follower lowpass filter which has a capability of bulk-attenuation cancellation in higher order is presented. Under strong inversion bias arrangement for high frequency application, this fourth-order-filter is simulated in a 0.18 μm standard CMOS process and exhibits a 20 MHz bandwidth with total power consumption of 0.323 mW from 1.8 V supply. Third order intermodulation distortion verification with 1.9 and 2.1 MHz signal archives 23.9 dBm IIP3 with 75.5 dB dynamic range. By using figure-of-merit as a benchmark indicator, the proposed filter is one of the top in its class with the lowest power consumption.

FD-SOI is a promising technology for integrating mm-wave front- end circuitry. In this paper, fully-differential SPST and SP4T switches are designed with wideband operation (DC up to 50 GHz) using GlobalFoundries’ 22FDX® platform. Based on a differential modeblocking topology, the switches can achieve isolations better than 50 dB. At 28 GHz, the balanced topology achieves an insertion loss of 1.92 dB, a 1-dB compression of 23.5 dBm and an IIP3 of 47.6 dBm.

The optimal transmitter position for maximum WIFI coverage in a residential home is investigated. A 60-GHz, 32 by 32 patch array antenna is implemented as the transmitter and the receiver antennas. The receivers are placed in each room of the home at equally spaced distances. The power received by each receiver is taken into account. By using genetic algorithm optimization in parallel, the optimal transmitter position is chosen as the one with the minimal number of receivers having received power less than −87.5 dBm. The GA chosen position results in acceptable received power at all but six receiver positions.

A Battery free ultra high frequency 0.9 GHz Radio Frequency ID applications, an extended RF energy collecting framework have planned and introduced. The proposed system incorporates a pi-matching organize off-chip UHF differential radio wire taken after by a CMOS cross-coupled RF-DC transformation rectifier that replaces a battery in various RFID applications. For a UHF band (900 MHz), the designed matching technique shows in differential to RF-DC converter gives a high efficiency of 64percentat -14 dBm. Utilizing CMOS UMC 0.18mum innovation, the proposed design accomplishes way efficient system for input control for -20 dBm to -4 dBm.

This paper presents a 314-344 GHz high output power push-push frequency doubler for radar applications with 1 dBm P sat at 324 GHz and 30 GHz P sat 3 dB–bandwidth. It is driven by a three-stage, cascode-based D-band driving stage, providing a differential saturated output power of 14.3 dBm at 154 GHz with a peak PAE of 4.5% and 13.4 dBm output referred P 1 dB . The chip is fabricated using a 130 nm SiGe BiCMOS technology with f t /f max of 250 GHz / 370 GHz. Thanks to the use of harmonic reflectors an overall peak conversion gain of 20 dB is achieved and remains above 6 dB at saturation.

The use of high carrier frequencies having wide bandwidth is expected to achieve high data rates in fifth-generation mobile systems and beyond. In heterogeneous networks (HetNets) that combine with macrocells and picocells in the same coverage area, picocells operating with high carrier frequencies are typically overlaid on macrocells using low carrier frequencies. A key technology for increasing data rates includes higher-order modulations such as the 256- and 1024-quadrature amplitude modulation (QAM). In this research, using a modulation and coding scheme (MCS) that incorporates 256- and 1024-QAM, we investigate the optimal transmission (Tx) power of a pico-evolved node B (eNB) for multiband HetNets combined with a macro-eNB using a carrier frequency of 2 GHz and pico-eNB having a wider signal bandwidth using 4.5 GHz. Under the assumption that the signal bandwidth of the pico-eNB is 10 times wider than that of the macro-eNB, we clarify the average and 5-percentile user throughput as a function of Tx power of the pico-eNB using system-level computer simulations. Based on these results, we confirm that the Tx power of the pico-eNB of 37 dBm can provide the best performance when the Tx antenna height is 10 m and the number of pico-eNB is four per macro-sector. Furthermore, it is shown that the use rate of both 256- and 1024-QAM in the downlink MCS reaches 11% when the Tx power is 37 dBm. This study will provide a remarkably effective solution for deciding the optimal Tx power of pico-eNB in multiband HetNets.

A 28 GHz watt-level CMOS SPDT switch with integrated electro-static discharge protection is designed and fabricated in a 65 nm CMOS process for a fifth-generation mobile communication. The measured insertion losses of the SPDT are 2.2 dB and 2.6 dB for transmit and receive modes, respectively. The fabricated SPDT switch shows output P1dB of >30 dBm for transmit mode and input P1dB of 4.3 dBm for receive mode.

A 88-100GHz stand-alone power amplifier and a 95-100GHz IQ combined power amplifier in 65-nm bulk CMOS are reported. The single PA is a 3-stage pseudo-differential CS design with transformers as matching networks, utilizing cross-coupled capacitive neutralization. The IQ PA utilizes the single PA core and uses a current combiner to sum two quadrature signals at the output. The single PA achieves 13.4 dBm saturated power with peak PAE of 11.6%. The IQ PA achieves 13 dBm of output power in QPSK constellations and offers a 360° phase control. Both designs use a 1.2 V supply.

In this paper, we propose an efficiency enhanced CMOS power amplifier (PA) at 28 GHz. This work is the first time using the cross-couple pair (CCP) to be the g m compensation technique to improve AM-AM distortion at the power stage. In addition, we also use the linearizer and adaptive bias to extend the linear power region and increase back-off efficiency. In order to improved PAE in wide input power range, the adaptive bias, linearizer, and g m -compensation are used for low/medium/high power regions, respectively. The peak gain is 22.72 dB and 3-dB bandwidth is 5.7 GHz. At P 1dB , the measured output power and PAE are 16.73 dBm and 21.37 %. The measured P sat and peak PAE are 17.68 dBm and 23.56 %. The measured back-off 6 dB PAE is 10.8 %. The total dc power consumption is only 97 mW for 1.2 V supply voltage. To our best knowledge, this PA has higher gain, better back-off PAE, and outstanding FoM.

A fully integrated Ku-band (14∼18GHz) self-biased bidirectional amplifier (BDA) is demonstrated in a $0.25\mu\mathrm{m}$ GaAs pHEMT technology. The proposed bidirectional amplifier comprises a power amplifier (PA) and a low noise amplifier (LNA) for T/R modules of phased array with in/output switches. In transmitting mode, the BDA achieves a flat small signal gain of $24.2\pm 0.8\ \text{dB}$ , the measured saturated output power is 23.6 dBm with 28.3% peak power added efficiency (PAE) at 16 GHz. In receiving mode, the BDA achieves a flat gain of $13.1\pm 0.7\ \text{dB}$ . The measured minimum noise figure is 4.2 dB at 16 GHz and below 4.7 dB over the band. And its in/output P1 dB are 10.3 dBm and 22.8 dBm at 16 GHz, respectively. The size of the MMIC is $2.15\ \text{mm}\times 1.55\ \text{mm}$ . To the authors' knowledge, this is the first demonstration of Ku-band self-biased BDA, and it attains state-of-the-art peak PAE in Tx mode, and in/output P1dB in Rx mode.

We examine fiber capacity per unit amplifier pump power relevant to power-constrained spatial-division-multiplexing submarine systems via extensive amplified transmission experiments and modeling. Our results suggest the utility of amplifier pump powers as low as 20 mW and output powers as low as 6.5 dBm.

A 25Gbit/s-class burst-mode receiver for 50G-EPON systems with a 25G APD and 25G burst-mode TIA, fabricated by $0.13-\mu m$ SiGe BiCMOS technology, achieves record high sensitivity of −27.7 dBm (OMA) at $BER=10^{-2}$ and record settling time of 150 ns.