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Condition monitoring of insulated gate bipolar transistor (IGBT) modules is an effective way to improve the transient performance and reliability of modular multilevel converters (MMC). This article proposes a novel bond wire failure monitoring method for the multichip IGBT modules in the MMC half-bridge submodule (SM) structure. The collector voltage undershoot VCA(np) of the complementary IGBT switch is measured during the turn-off switching transition of the controlled IGBT switch. VCA(np) is sensitive to the induced voltage over the stray inductance of the IGBT bond wires and provides high sensitivity as a health indicator. The non-intrusive measurement technique is demonstrated using a half-bridge circuit during the turn-off transition of the controlled IGBT, while its complementary switch (i.e., the device under test) is in the off state. Theoretical analysis and experimental results show that the parametric drift due to wire bonding failures can be effectively monitored with high specific relative sensitivity and granularity. To ensure its effectiveness in practical applications, the influence of load current, SM capacitor voltage, and junction temperature is discussed. In addition, a readout circuit is designed featuring the integrated desaturation detection and voltage peak detection, which offers both the short-term overcurrent fault protection and long-term bond wire aging monitoring functions. [ABSTRACT FROM AUTHOR]

Due to the lack of alternating electric fields and alternating magnetic fields in HVdc transmission system, there has been no sustainable and stable energy harvesting method compatible with them up to now, hindering the application of HVdc sensors. In this letter, we proposed a novel dc energy harvesting method using corona current, and an energy harvesting circuit is constituted with space ion flow generated by dc corona. The feasibility of the proposed method is increased by adding an artificial corona electrode and placing the load before the corona electrode. In addition, it can flexibly operate at any position in an HVdc transmission system according to actual demand. Then the output power is further maximized by adopting a capacitor with high working voltages. The detailed measurement results based on the experimental system validate the effectiveness of the proposed method, with a stable output power as high as 10.15 mW in a dc system of 22 kV. A detailed discussion of the overall performance is finally carried out. [ABSTRACT FROM AUTHOR]

Unbalance of transient currents of multiple chips inside press-pack insulated-gate bipolar transistor (PP IGBT) results in degrading operation and even device damage. Chip currents measurement plays an essential role to understand and solve this problem. Printed-circuit board Rogowski coil (PCB RC), as a small, noninvasive, and high bandwidth current sensor, is very suitable for this application. However, PCB RC integrated with multiple Rogowski coils (RCs) is still difficult to be applied to measure the current of multiple chips in press pack IGBT device because of the low measurement accuracy due to the large interference. In this letter, a high accuracy PCB RC with ten rectangular RCs inside PP IGBT is proposed to measure ten chip currents at the same time. Different from single RC measuring single chip current, the interference of adjacent chip currents has to be considered, and is reduced to 0.6% by optimizing the turns arrangement and lead wires of RCs. The noise of cross talk of adjacent RCs is 1.7% by decreasing the capacitance coupling between RCs. Shielding layers and grounding patter of lead wires for ten RCs are proposed to eliminate the interference of collector voltage. The experiment of transient process of ten chips verifies the effectiveness of proposed PCB RC, and measurement error is only 1.8%. [ABSTRACT FROM AUTHOR]

Turn-off failure under clamped inductive load, is one of the most concerns in insulated gate bipolar transistor (IGBT) chips. Besides, this turn-off failure can be attributed to two causes, i.e., the dynamic latch-up and the secondary breakdown. Despite great simulation work investigated previously, the experimental research should be further focused. Up to now, the typical features and differences for these two turn-off failures still remain unclear. In this article, two failures’ waveforms are first compared in experiment. Moreover, their internal current, electric field, and temperature distributions are compared by simulation in detail. Then, two different failure features, focusing on the failure cell structures, are summarized from the scanning electron microscope (SEM) results for the first time. The marked signatures of these failures, such as the current filament path and the mixture region, are further analyzed in this article. According to the SEM results, the lateral and vertical current paths can be observed in dynamic latch-up chip and secondary breakdown chip, respectively. These failure signatures in waveforms and SEM results can contribute to the distinguished method to the failure causes in IGBT device, and enhance the chip's performance more effectively. [ABSTRACT FROM AUTHOR]

Press-pack insulated gate bipolar transistor (IGBT) devices have multiple chips paralleled to enhance their power density. However, the current imbalance among chips limits the increase of the power, which is mainly attributed to external factors, like stray inductance, temperature, and mechanical pressure. Besides, for the difficulties in decoupling multiple external factors, the current imbalance in press-pack IGBT devices has been extensively studied by simulation, and lack of experimental investigations. In this article, a multifactor decoupling experimental approach for the current sharing characteristics is proposed. The stray inductance, temperature, and mechanical pressure of the two parallel branches can be adjusted independently for investigating chips’ current sharing. Then, the experimental platform for the parallel 3.3 kV/50 A IGBT chips under differentiated external factors is implemented. Measured results show that the stray inductance affects the transient current sharing during turn-on greatly, and the maximum current imbalance can reach 25.46%. The temperature mainly affects the steady state and the maximum current imbalance is 11.7%. Otherwise, mechanical pressure is negligible on the steady and transient current imbalances, which are less than 3%. Finally, the influence mechanisms of the external factors are proposed to explain the current sharing characteristics of parallel chips. [ABSTRACT FROM AUTHOR]

Current sensor integration provides many benefits on the power density and reliability of power modules. However, existing current sensors are not suitable for the integration in silicon carbide power modules. This article proposed a low temperature co-fired ceramic (LTCC) based low profile current sensor with mount-ready structure. The current capacity, bandwidth, electrical insulation, and thermal expansion performance of the proposed current sensor are fully analyzed and evaluated. The mutual inductance between the designed sensing coil and current carrying conductor is 4nH with a relative error less than 5% compared with finiteelement analysis simulation results. The dynamic current measuring accuracy is verified by double pulse test. The error of first peak measurement is reduced from over 20% to less than 5% by changing the commercial Rogowski coil to the proposed LTCC current sensor. The wide temperature test results show that the proposed current sensor can be applied in high temperature environment conditions. [ABSTRACT FROM AUTHOR]

Partial discharge which often occurs at channel stopper of high voltage chip will cause insulation damage of chips which is harmful to the device application. Thus, it is important to improve the whole design to promote chip insulation capacity. In this brief, a novel chip surface shielding structure named U-protector is proposed which can promote the insulation capability of high voltage chips. Through the simulation, it can be found that the maximum electric field strength of chips can decrease 8% with adding U-protector. Moreover, verified by experiments, the partial discharge initial voltage (PDIV) of chips with U-protector can be promoted about 6.1%–12.7% of rated voltage. Furthermore, the universality and practicality of this structure are also investigated which can be used in multiple high voltage chips. [ABSTRACT FROM AUTHOR]

A low-cost mechanical circuit breaker (MCB) is an important solution in the field of dc breaking. However, the zero-crossing points in the breaking process of the existing MCBs are either insufficient in number or slow in generation, which limits the breaking performance of MCBs. This letter proposes a novel forced resonant MCB (FR-MCB). A large number of zero-crossing points can be generated in a short time by utilizing a resonant circuit and a power electronic-based auxiliary oscillation switch. Thus, the FR-MCB can exhibit more reliable and faster breaking performance while maintaining the low cost. After the detailed analysis of current oscillation and breaking process in the FR-MCB, a prototype experiment of up to 10 kV/8 kA is conducted to verify its feasibility. [ABSTRACT FROM AUTHOR]

The diode bridge submodule (SM) is one of the basic units of a hybrid high-voltage dc circuit breaker. This article works on the low inductance design of a single SM and series SMs. For the layout design of a single SM, this article proposes a simple and clear +-shaped SM layout, the low inductance design is simplified to the optimization of two laminated busbars with a simple structure. Based on the +-shaped SM layout, this article further proposes an SM structure with holes in diodes region, the stray inductance is further reduced, and only one integrated laminated busbar is needed in a single SM. For the layout design of series SMs, this article makes full use of the layout of a single SM and the mutual inductances between the SMs, series SMs are alternately connected in reverse. The single SM layout proposed in this article is effective in reducing the stray inductance. The loop stray inductance in stage II reduced from 148.4 to 72.3 nH, a 51.3% reduction. When the two parallel IGBTs turn off a 6 kA fault current in 2 μs, the voltage spike is reduced from 786.1 to 423.4 V, a 46.1% reduction. And the stray inductance difference of the bidirectional current path is controlled to about 10 nH. The layout of series SMs proposed in this article is effective in reducing the length of the series SMs, the length is reduced by 16.7%. The experimental results show that the SMs layout proposed in this article is effective. [ABSTRACT FROM AUTHOR]

PEEK (Polyetheretherketone) and N2 are used as the frame material and insulation gas in the packaging of high voltage power electronic devices, respectively. Considering the IGBT device in normal operation, the chip will produce a large amount of Joule heat, which will increase the temperature of the insulation material in sub-modules. However, there has been no investigations on the influence of temperature on the surface discharge characteristics and mechanisms under positive repetitive square voltage (PRSV). In this paper, surface discharge current pulses and optical photos of surface streamer propagation of PEEK in N2 at different temperatures are collected under PRSV. The effects of different temperatures on discharge current pulse, charge quantities of discharge and time delay of discharge are analyzed in detail. Besides, the surface trap parameters at different polarization temperatures are measured by TSDC. The effects of temperature on the effective ionization rate, surface trap depth and densities are revealed. A reasonable model is used to explain the role of surface traps in the streamer propagation along the surface of PEEK. Besides, the time delay theory is introduced to quantitatively analyze the effect of temperature on the time delay of forward discharge (FD) and backward discharge (BD). The influence mechanism of temperature on specific pulse parameters of discharge current, time delay of discharge and charge quantities of discharge are all analyzed on the basis of the trapping and detrapping of surface electrons and ions at different temperatures. [ABSTRACT FROM AUTHOR]

In the conventional partial element equivalent circuit (PEEC) method, all partial inductances are connected at both ends to other circuit elements of a PEEC or modified nodal approach (MNA), simulation program with integrated circuit emphasis (SPICE) type circuit. This article shows that if at least one end of a partial inductance remains without a connected element, it is called an open loop, which is also physical and is theoretically closed by displacement current. It is shown in this article that the open loop is only consistent if the partial inductance is evaluated using the Coulomb gauge; else, the magnetic energy computation of open loop is inconsistent. This article focuses on the difference and presents an analytical method for the calculation of partial inductance with Coulomb gauge in quasi-static field to figure it out. This difference is proven to be related to the calculation of vector potential A, whereas existing calculation is based on Lorentz gauge. Then, analytical results of conductor segments are derived for comparison of the two different gauges, and show the difference. Also, numerical experiments of the self- and mutual-partial inductances of conductor segments in open-loop problems are given for further comparison. The results illustrate that the proposed method is consistent with magnetic energy, and could be directly be applied to closed-loop problems without affecting the validity of the PEEC method. This method is believed to be an effective supplement in physical sense of partial inductance. [ABSTRACT FROM AUTHOR]

The printed circuit board Rogowski coil (PCB RC) has been widely applied in the complex electromagnetic environment, such as power electronic devices, where it is placed outside but very close to current-carrying conductors; thus, this brings great challenges to the anti-interference ability of it. Generally, the anti-interference ability of PCB RC is greater with more turns; however, the number of turns is limited by two aspects: the one is the bandwidth of PCB RC, which is reduced as the turns increase, and the other is the minimum distance between vias, which is determined by process technology. This article proposed a method of segmented turns arrangement of PCB RC to acquire better anti-interference ability almost without lowering the bandwidth and get closer to the technical limit of distance between vias. The segmented turns are designed to be stair-stepping rather than rectangular used in traditional integral turns, which is equivalent to splitting a complete rectangular turn into several small rectangular turns so that the turns density is increased with the anti-interference ability improved. As an example of the method, a square PCB RC with proposed segmented turns is designed and compared with the PCB RC with traditional integral turns, and the results of calculation and experiment show that the anti-interference ability of PCB RC with proposed segmented turns is enhanced to be doubled and very great even near the corner of the PCB RC. [ABSTRACT FROM AUTHOR]

The circular Rogowski coil with a rectangular section is the most common and basic measuring unit of current. However, in some situations, a noncircular Rogowski coil is more suitable because of the limited space to be embedded in and the demand for decreasing the size of the Rogowski coil. Circular Rogowski coil is usually wound uniformly to guarantee the positional accuracy and anti-interference ability considering the very good symmetry. However, for noncircular Rogowski coil, the turns arrangement is usually designed based on experience due to the lack of theoretic direction. This article first proposed a method of turns arrangement of the noncircular Rogowski coil with a rectangular section, which the positional accuracy and anti-interference ability can be achieved at the same time. By establishing the equivalent relation between mutual inductance and electric potential, the turns density of the noncircular Rogowski coil can be acquired by solving the charge density on its equivalent electrodes. The turns density is proven to be unique. For a given turn number, the turns arrangement of the noncircular Rogowski coil can be obtained by discretizing the turns density. As an example of the method, a square Rogowski coil, which can be used in chip current measurement in Press Pack insulated gate bipolar transistors (IGBTs), is particularly designed and contrasted with the traditional square Rogowski coil with turns equidistantly arranged to verify the great positional accuracy and anti-interference ability. The results of the calculation and experiment show that this method is very effective. [ABSTRACT FROM AUTHOR]

Metal oxide varistors (MOVs) are usually applied to clamp the voltage across a dc circuit breaker (DCCB) after fault current elimination. This letter focuses on the transient process of a DCCB turn-off and has three contributions. First, it reveals that snubber circuit inductance, the internal and external stray inductances of an MOV could cause a significant overvoltage across a DCCB, which exceeds 47.5% of its nominal clamping voltage. The overvoltage mechanism is clearly analyzed based on the working principle of a DCCB, providing theoretical equations to estimate the overvoltage magnitude. Second, a nonlinear model of an MOV is proposed to simplify the calculation and provide an accurate estimation result. Third, a new arrangement of series submodules with discrete MOVs is proposed to suppress the overvoltage. A hybrid 500 kV/25 kA DCCB prototype with series insulated gate bipolar transistors (IGBTs) is implemented to validate the proposed analysis. The series-IGBT rating voltage is 1440 kV, and the MOV with a nominal clamping voltage of 800 kV is used to protect IGBTs. However, a 25 kA turn-off experiment clearly shows that the overvoltage increased to 1203 kV by an external stray inductance of 39.5 μH and di/dt of 1480 A/μs. The relative error between measurements and simulations is within 3%. Besides, simulations on the new arrangement show the overvoltage is decreased by 23.4% than before. [ABSTRACT FROM AUTHOR]

Plasma extraction transit time (PETT) oscillation will cause electromagnetic interference, which is harmful to the device operation. Thus, it is important to estimate the PETT oscillation frequency accurately to suppress this oscillation. While the existing formula for PETT oscillation frequency is approximate due to its divergent problem, in this letter, a modified formula for PETT oscillation frequency is proposed for insulated gate bipolar thyristor devices. The modified formula considers the acceleration process, which is complex but does not change with the electric field. Therefore, the divergence of the formula can be well solved by introducing the modified term. Moreover, the modified formula can be obtained straightforwardly and well match the measured oscillation frequency, which verifies the accuracy of the proposed formula. [ABSTRACT FROM AUTHOR]

In this article, a sequential Vce(T) method with separated gate controller is proposed to measure the junction temperature distribution within press-pack insulated gate bipolar transistors (PP IGBTs), which is not possible for traditional temperature measurement methods due to the enclosed structure and external clamping force of the pressure-type package. This proposed method is integrated into a standard dc power cycling test and the steady-state junction temperature distribution is obtained to validate its applicability and effectiveness. The measured junction temperature exhibited a bathtub type distribution within PP IGBTs. The root cause is the deformation of the copper plate, which was also discussed by the finite-element simulation in previous literature. Furthermore, the influence of static characteristic dispersion is excluded by the chip transposition and the thermomechanical coupling effect is confirmed to be the dominant factor of this junction temperature distribution. Finally, the influence of heating current and heating time on junction temperature distribution is also investigated by the proposed method. [ABSTRACT FROM AUTHOR]

Plasma extraction transit time (PETT) oscillation occurs when insulated gate bipolar transistor (IGBT) devices turn off, whose frequency can reach hundreds of MHz. This high-frequency oscillation can induce electromagnetic interference problems and may exceed relevant IEC limits for electromagnetic emission. As one of the electromagnetic disturbance sources from internal IGBT, the PETT oscillation has not attracted much attention in the electromagnetic compatibility (EMC) problems of application and development of high-voltage IGBT devices yet. In this article, the detailed characteristics of PETT oscillation, i.e., oscillation frequency, duration time, and oscillation peak, in high-voltage IGBT devices are systematically investigated by experiments. From the results, oscillation frequency increases with the increase of reverse voltage, whereas decreases with the increase of the temperature. Then, more complex dependencies of the PETT oscillation characteristics on IGBT's commutation conditions are presented. It is shown that its characteristics vary greatly under different reverse voltage, forward current, and temperature. The hazard of PETT oscillation to electronic components is discussed as well. PETT oscillation occurs during the turn-on process, which is first reported. Based on the experiment results, the EMC test related to PETT oscillation is suggested to be performed under different commutation conditions. [ABSTRACT FROM AUTHOR]

In this paper, the surface discharge current pulses of PEEK (polyether-ether-ketone) under positive repetitive square voltage are measured. The effects of voltage rise time and fall time on pulse parameters of discharge current, instantaneous voltage of discharge and time-lag of discharge are analyzed in detail. The results show that the amplitude of discharge current and the instantaneous voltage of discharge decrease, and the time-lag of discharge and the dispersion of time-lag increase with the increase of voltage rise time. With the increase of voltage fall time, the amplitude of discharge current decreases and the instantaneous voltage of discharge, the time-lag of discharge and the dispersion of time-lag increase. To analyze the influence mechanism of voltage rise time and fall time on surface discharge, the accumulation of surface charge under repetitive square voltage is regarded as a periodic process. Besides, the correlation between forward discharge and back discharge in the process of discharge is analyzed, and the development of discharge is analyzed by using the time-lag theory. Furthermore, the relationship between instantaneous discharge voltage and voltage slew rate is revealed, and the surface charge accumulation processes under different voltage rise times and fall times are compared to reveal the influence mechanism of rise time and fall time on the surface discharge under positive repetitive square voltage. [ABSTRACT FROM AUTHOR]

In the HVdc circuit breaker testing process, a thyristor is used to generate high current for the testing purpose. However, the reverse recovery process (RRP) of a thyristor can induce a significant overvoltage problem, which jeopardizes the reliable operation. It is important to model the RRP of a thyristor. The existing modeling methods usually omit the stray inductances in the circuit, which cannot describe the hard-switching process accurately. Therefore, this article proposes a novel method to model the RRP, considering the stray inductances. There are mainly three original contributions. First, the physical mechanism of the RRP is analyzed, describing the internal charge behavior and dividing the RRP into two stages. Second, this article provides a novel trigonometric exponential (TE) model of the thyristor voltage and current with analytical equations. Third, the extraction method of model parameters is also provided based on external circuit parameters and thyristor characteristics. In order to verify the proposed modeling method, a 1 kV/830 A IGBT-based circuit breaker is implemented with a thyristor to initialize the current. The experimental results show that the negative peak voltage induced by the RRP is as high as 4.26 kV, and the proposed TE model can precisely predict the overvoltage with a relative error of 7.51%. [ABSTRACT FROM AUTHOR]

Extraction of the current commutation loop (CCL) inductance is necessary for the overvoltage analysis of power devices. In general, each transient process of a converter corresponds to a specific CCL. However, there is no such single CCL in the full-bridge module in hybrid dc circuit breakers during the turn-off transient. First, this article proposes a coupled inductance model of full-bridge modules. The model has less number of inductance compared to the traditional partial inductance model. Second, this article proposes the extraction method of inductances that can be easily obtained by both simulation and measurement. Moreover, the measured overvoltage waveforms of insulated gate bipolar translators (IGBTs) in the full-bridge module agree with the simulation results. Third, we propose an equivalent circuit of the series full-bridge modules in a 500 kV hybrid circuit breaker based on the proposed coupled inductance model. The mutual inductances among different modules are considered due to the compact structure of the series modules. The measured results show that the overvoltage of the IGBT in the series module could be well-predicted by the proposed equivalent circuit. [ABSTRACT FROM AUTHOR]