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Your search keyword '"Cristoloveanu, S."' showing total 424 results
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424 results on '"Cristoloveanu, S."'

1. 3D sequential integration: applications and associated key enabling modules (design & technology)

Author

Batude, P., primary, Billoint, O., additional, Thuries, S., additional, Malinge, P., additional, Fenouillet-Beranger, C., additional, Peizerat, A., additional, Sicard, G., additional, Vivet, P., additional, Reboh, S., additional, Cavalcante, C., additional, Brunet, L., additional, Ribotta, M., additional, Brevard, L., additional, Garros, X., additional, Frutuoso, T. Mota, additional, Sklenard, B., additional, Lacord, J., additional, Kanyandekwe, J., additional, Kerdiles, S., additional, Sideris, P., additional, Theodorou, C., additional, Lapras, V., additional, Mouhdach, M., additional, Gaudin, G., additional, Besnard, G., additional, Radu, I., additional, Ponthenier, F., additional, Farcy, A., additional, Jesse, E., additional, Guyader, F., additional, Matheret, T., additional, Brunet, P., additional, Milesi, F., additional, Van-Jodin, L. Le, additional, Sarrazin, A., additional, Perrin, B., additional, Moulin, C., additional, Maitrejean, S., additional, Alepidis, M., additional, Ionica, I., additional, Cristoloveanu, S., additional, Gaillard, F., additional, Vinet, M., additional, Andrieu, F., additional, Arcamone, J., additional, and Ollier, E., additional

Published
2021
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15. Improved Retention Characteristics of Z2-FET Employing Half Back-Gate Control.

Author

Kwon, S., Navarro, C., Gamiz, F., Galy, P., Cristoloveanu, S., Kim, Y. -T., and Ahn, J.

Subjects
IMPACT ionization, FIELD-effect transistors, RF values (Chromatography), DYNAMIC random access memory, POTENTIAL barrier, ELECTRON impact ionization
Abstract

The structure of zero impact ionization, zero subthreshold swing field-effect transistor (Z2-FET) has been modified by stacking a half side of back-gate (BG) with a heavily doped silicon layer instead of full covered BG. Through the modification, the memory window and retention time are significantly improved. For the modified Z2-FET, the retention time of “0”-state increases from 800 μs to 800 ms by reducing the read voltage from 1.1 to 1.0 V compared to the conventional Z2-FET. The simulation results show that the half BG helps the potential barrier to sustain the “0”-state longer without the potential collapse. The modified devices have wider memory window and larger sense margin than the conventional Z2-FET with full covered BG. [ABSTRACT FROM AUTHOR]

Published
2021
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16. Deep-Depletion Effect in SOI Substrates and its Application in Photodetectors With Tunable Responsivity and Detection Range.

Author

Arsalan, M., Liu, J., Zaslavsky, A., Cristoloveanu, S., and Wan, J.

Subjects
PHOTODETECTORS, METAL oxide semiconductor field-effect transistors, LOW voltage systems, TRANSIENT analysis
Abstract

We present an interesting transient effect found in silicon-on-insulator (SOI) transistors, where the drain current responds slowly to a back-gate voltage (VBG) pulse. This transient mechanism is due to the deep-depletion region in the SOI substrate induced by the VBG pulse and has been validated by experimental and TCAD simulation results. The deep-depletion characteristic can be employed for photodetection in a fully depleted (FD)-SOI MOSFET device. We have measured the photoresponse of the FD-SOI MOSFET under various light illumination conditions and studied systematically the impact of the VBG pulse duty ratio, amplitude, and period on the responsivity and detection range. An optimized device structure, fabricated in an advanced ultrathin body and buried oxide (BOX) (UTBB) SOI technology, shows low operation voltage and extended detection range. [ABSTRACT FROM AUTHOR]

Published
2020
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17. Memory Operations of Zero Impact Ionization, Zero Subthreshold Swing FET Matrix Without Selectors.

Author

Kwon, S., Navarro, C., Galy, P., Cristoloveanu, S., Gamiz, F., Ahn, J., and Kim, Y.-T.

Subjects
IMPACT ionization, ELECTRIC potential, POTENTIAL barrier, MEMORY, INDUCTIVE effect, QUANTUM gates, HIGH voltages
Abstract

This work experimentally demonstrates the memory operations of a $\text{Z}^{{2}}$ -FET (Zero impact ionization, Zero subthreshold swing) matrix without the use of selectors. Selection and deselection of memory cells in the same bit line can be controlled by modulating the front-gate voltage to prevent the use of a dedicated selector. Appropriate drain voltages to achieve two logic states need to be chosen according to the memory window when the cells are selected. 2D TCAD simulations reveal that the ‘1’-state current of a deselected cell remains as low as that of the ‘0’-state since the deselection gate voltage induces higher potential barriers that block the carrier injections from the source and drain. The power consumption for writing and reading the ‘0’-state are nearly identical for cells with and without selectors. However, at fixed bit line current, the power consumption in any writing and reading is slightly higher with selectors due to their voltage drop. [ABSTRACT FROM AUTHOR]

Published
2020
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22. A New Photodetector on SOI

Author

Liu, J., primary, Caol, XY., additional, Lu, BR., additional, Chen, YF., additional, Zaslavsky, A., additional, Cristoloveanu, S., additional, Bawedin, M., additional, and Wan, J., additional

Published
2018
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25. Evaluation of thin-oxide Z2-FET DRAM cell

Author

Navarro, S., primary, Lee, K. H., additional, Marquez, C., additional, Navarro, C., additional, Parihar, M., additional, Park, H., additional, Galy, P., additional, Bawedin, M., additional, Gamiz, F., additional, and Cristoloveanu, S., additional

Published
2018
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34. The mystery of the Z2-FET 1T-DRAM memory

Author

Bawedin, M., primary, El Dirani, H., additional, Lee, K., additional, Parihar, M.S., additional, Lacord, J., additional, Martinie, S., additional, Le Royer, C., additional, Barbe, J.-Ch., additional, Mescot, X., additional, Fonteneau, P., additional, Galy, Ph., additional, Gamiz, F., additional, Navarro, C., additional, Cheng, B., additional, Asenov, A., additional, Taur, Y., additional, and Cristoloveanu, S., additional

Published
2017
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36. First SOI Tunnel FETs with low-temperature process

Author

Diaz Llorente, C., primary, Le Royer, C., additional, Lu, C-M. V., additional, Batude, P., additional, Fenouillet-Beranger, C., additional, Martinie, S., additional, Allain, F., additional, Vinet, M., additional, Cristoloveanu, S., additional, and Ghibaudo, G., additional

Published
2017
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