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In this paper a comprehensive procedure for the analog modeling of Fractional-Order Elements (FOEs) is presented. Unlike most already proposed techniques, a standard approach from classical circuit theory is applied. It includes the realization of a system function by a mathematical approximation of the desired phase response, and the synthesis procedure for the realization of basic fractional-order (FO) one-port models as passive RC Cauer- and Foster-form canonical circuits. Based on the presented one-ports, simple realizations of two-port differentiator and integrator models are derived. Beside the description of the design procedure, illustrative examples, circuit diagrams, simulation results and practical realizations are presented.

The understanding of circuit diagram is very important for the study of electrical engineering. Existing circuit diagram simulation tools are mostly based on GUI interface and rely on users to click or drag icons with mouse, which requires them to be familiar with the software and distracts a great deal of their attention from the circuit diagram itself. Although a lot of previous works have devoted to designing algorithmic solution to recognize hand-drawn circuit diagrams automatically, there still exists strict constraints on users’ drawing habits and stroke orders. In order to address these inconveniences, this paper proposes a novel sketch recognition algorithm named $LS^{4}D$ . It uses graph to model the input strokes and their relationships, and leverages cycles by local strokes to detect some circuit components. Theoretical derivations have demonstrated that $LS^{4}D$ can efficiently recognize diagrams with different drawing styles and arbitrary stroke orders. To furthermore illustrate the practical value of the proposed approach, we construct a prototype of pen-based circuit diagram system based on $LS^{4}D$ , which enables users to draw circuit diagrams directly on the digital screen without any other restriction. An experiment of 158 samples collected from 17 users is conducted on the designed platform. Our approach has achieved 93.04% recognition accuracy and overall 4.53 from a 5-scale user satisfaction rating, which outperforms previous state-of-the-art methods numerically. It is shown that the same approach can also be generalized to many other sketch recognition applications with minor modifications. To facilitate future researches and applications, we publish our source code, model, and training data at https://github.com/Huage001/ Graph-Based-Circuit-Painter.

Discuss the problem of airport security check process based on circuit diagram. The efficiency of the airport security check to a certain extent determines the flight delay or not. This paper establish the circuit diagram model with the knowledge of electronics which depicts vividly the general process of airport security check as well as qualitatively and quantitatively analyzes the difference of passenger flow during the trough and peak period. What’s more, the model also finds out where the choke point that affects the efficiency of security check is located. So this study has some reference value for directional research on practical issues.

The process of converting a small city car with an internal combustion engine into an electric vehicle is described. The main stages in the selection of the main units and how they function are presented. The circuit diagrams and battery charge management software are presented. Generalizations are made concerning the performance parameters of the electric vehicle.

Power electronic based high frequency DC-DC converter have several industrial and research applications including its use in electric vehicles for fast charging of battery. In this paper the design and simulation of single phase DC-DC converter capable of converting 500 volt DC into 24 volt DC and delivering nominal power of 250 Watts and surge power of 1 kW up to 60 msec for industrial load has been described. A high quality, reliable, efficient and compact converter power source with complete isolation between source and load is required for continuous operation. The compactness of Switched Mode Power Supply (SMPS) system depends upon size of high frequency transformer and filter requirements. The magnetic components in converter circuit such as transformer and inductors may be designed smaller in size by increasing the switching frequency of the converter. The switching frequency for proposed converter is chosen 100 kHz. A comparative analysis of various topologies of DC-DC converter has been explained to select appropriate control topology for desired application. The proposed design is based on Phase Shifted Full Bridge (PSFB) technique utilizing power Silicon Carbide (SiC) MOSFET switches, a center-tapped transformer and a Digital Signal Processor (DSP) based control system. The converter design comprised the front-end of a full bridge DC-AC square wave inverter using phase shifted Pulse Width Modulation (PWM). The paper describes design considerations and circuit schematic configuration of DC-DC converter. Circuit simulation models for proposed converter and simulation results have been presented for comparison of various performance parameters

Under Emerging Engineering Education circumstances, this paper aims to cultivate the learning interest and strengthen the engineering practice ability of first-year students majoring in automation and control by making a self-leveling quadrotor. Firstly, the attitude calculation based on complementary filtering and the PID control algorithm based on a quadrotor altitude control case is intuitively explained. Furthermore, this paper guides students to utilize Arduino Uno and MPU-6050 to implement the PID control program and attitude calculation program step by step. Finally, the essential hardware and the circuit diagram are given to build a self-leveling quadrotor. This paper can be used as an introductory course for automation and control majors, mainly to stimulate students’ interests and establish students’ systematic design thinking and hardware and software coordination ability.

New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.

Series connected Si MOSFETs provide a useful method to achieve greater voltage blocking capabilities in high-voltage power converter applications. However, the challenge imposed using this method is a naturally unbalanced voltage between series stacked devices. Voltage sharing imbalance can occur due to gate signal timing delay, device tolerances and layout parasitics potentially leading to overvoltage for a given device and subsequent converter failure. This article introduces a novel voltage balancing technique with additional transient voltage suppressor devices (TVS) to improve the reliability of 3-level bridgeless totem-pole (BTP) flying capacitor multilevel (FCML) converter comprised of low-voltage silicon based MOSFET devices. Relevant circuit diagrams and experimental results are both provided using a universal 9A-input current industrial PFC prototype converter.

In this research work a 10 bit SAR(Successive Approximation Register) type ADC(Analog to Digital Converter) IP(Intellectual Property) has been approached with some specifications along with the circuit diagram of each elementary design block. Here 180 nm technology has been used. Various types of performance parameters like area, resolution, i/p current, i/p impedance, conversion time etc. have been discussed. Also the pre-layout as well as post layout simulation results have been given in this paper.

Building electronic circuits is one of the most common hands-on activities in learning STEM subjects. Beginning students often find it difficult to translate a circuit schematic into the construction of the physical circuit on a breadboard. In this paper, we describe an Augmented Reality circuit learning software that can provide students with step-by-step instructions by placing virtual circuit components on a physical breadboard. We propose a novel image processing pipeline that can robustly identify the planar structure of a breadboard, even in the presence of occluding circuit components on the breadboard. Using a commercially available library of 3D circuit component models, the estimated 3D structure of the breadboard allows us to render arbitrary circuit components on it in real time. Experimental results demonstrate that our algorithms are accurate and can produce realistic-looking virtual circuits.

It is well known that the mathematical modeling and manual computations of the transistor design parameters are sometimes impractical and remains a challenge for researchers. In submicron technologies, the basic component of a three-stage operational amplifier such as MOSFET is modeled by various complex nonlinear equations. The modeling equations include parameters such as channel length (L), channel width (W), node voltages, and branch currents. However, the design and analysis of such complex nonlinear equations are depending on the expertise of the designer. In this paper, a Neural network is used to design and implement a three-stage operational amplifier. The channel length (L) and width (W) which are most suitable for circuit characteristics are calculated using neural network training. The Cadence tool is used to simulate the various circuit diagrams. The Neural Network model is developed and trained using MATLAB 2019b software platform. The effectiveness of the proposed neural network model is tested using the various circuits.

This paper designs a connection of a new large-scale solar farm (160 MW) to an existing 230 kV system (based on the IEEE 9 bus system). Regarding the choice of connecting the solar farm to Bus, this paper respectively gives the analysis of Bus5, Bus6 and Bus8, and draws the conclusion that connecting Bus5 is the best choice. When designing the transmission line, this paper gives the shortcomings of tower type B and tower type C, analyzes the reasons for choosing tower type A, and analyzes the various parameters of 5 different conductors. The best conductor choice is 16.33 mm wire, the best conductor bundling option is bundling spacer – 2 conductors. Then, this paper used PowerWorld to simulate the circuit diagram of the IEEE 9 bus system, and carried out power flow analysis and system safety analysis on the power system. It is recommended to connect the transmission line in parallel between Bus5 and Bus7 and between Bus4 and Bus5 to enhance the safety and stability of the system. When any one of the transmission lines is disconnected, the remaining transmission lines will not overcurrent and can work safely. Finally, this paper analyzes the total cost of the design from three aspects: new transmission lines, parallel conductors of old transmission lines, parallel capacitor and inductor, and calculates the total cost is $1,405,398,400.

Photovoltaic (PV) sources are inherently nonlinear power devices and maximum power derivation depends on Maximum Power Point Tracking (MPPT) algorithms. The algorithms require testing in real time situation using PV source which will be troublesome due to higher dependency on environmental factors and larger space requirements for higher power rating. The increased and faster testing lead to develop a PV emulator with desired performance and lower price compare to the commercially available PV emulators. In this paper, design of a digitally controlled PV emulator with varying resistive load is proposed to replicate the behaviour of real PV sources. The power stage of the PV emulator is realized using dc-dc buck converter topology and the controller stage uses an algorithm-in-loop Newton-Raphson (NR) method. Finally, the PV emulator is tested with MPPT controlled dc-dc boost converter for battery charging. The design of the power and control stages of the PV emulator has been compared with the real PV source and it is observed that the obtained V-I characteristic is in good agreement. Moreover, an analysis is presented for different switching frequencies of the boost converter connected as load to the fixed switching frequency buck converter, i.e., PV emulator. Further, a schematic hardware circuit diagram has been given to realize the proposed digitally controlled PV emulator.

Embedded applications with requirement of portability need rechargeable battery. A novel DC Uninterruptible Power Supply (UPS) system with battery charging and battery’s State of Charge (SOC) monitoring system has been proposed in this paper. DC UPS systems are evolved in recent times due to requirement of fewer power conversion stages as compared to traditional UPS. This paper describes the DC UPS circuit which transits instantly and automatically from external power supply to battery source and vice versa when external power supply is removed and applied respectively. Modes of operation of DC UPS are explained in this paper. Proposed circuit uses rechargeable battery and thus, a battery charging circuit and battery's SOC estimation circuit are part of the proposed circuit. Battery’s SOC is estimated by Coulomb counter method. Charging circuit diagram and designing of its components are explained. SOC estimation is based on integrating current through the battery, which is done by coulomb counter - LTC4150 which is interfaced with a micro-controller. Initial SOC estimation is one of the important tasks while implementing coulomb counter method. It is estimated by measuring Open Circuit Voltage (OCV) of battery and mapping it to get corresponding initial SOC. Proposed circuit is designed in such a way that, if battery voltage reduces to 3.3V while discharging, circuit disconnects battery from system till external supply is available to charge the battery. Microcontroller is programmed to calculate and display Initial SOC, SOC, and battery voltage on serial monitor.

The laser direct imaging exposure machine directly images the CAM data on the printed circuit board (PCB) substrate, thus do without film procedures in the exposure process, reducing the deviation caused by film expansion and undergo distortion during fabrication, and improving the productivity of PCB production. As the line width of the circuit diagram continues to become smaller, a smaller spot is required to expose a small line width, but because the laser spot size cannot be reduced without limit, the circuit diagram line width is reduced to smaller than the spot, which will cause insufficient exposure accuracy. It is the main motivation of the present invention to use a larger laser spot size to expose a small line width, and to improve the accuracy of the circuit line diagram. Based on this, this paper proposes a laser source target light dose reversed mapping output strategy. Through trial exposure, the initial spot position map, connected component labeling (CCL) and parallelized 0-1 integer programming are found out laser spot exposure position map, are reconstructed with a new spot distribution. It can achieve the accuracy requirement of exposing small line width and line spacing with a twice laser spot size. In addition, the mathematical calculation amount of the target light dose reversed mapping are very huge matrix, and calculating the image pixels point by point is very time-consuming. This paper proposes a method to effectively reduce the amount of calculation and acceleration.

In current operation and maintenance work of smart substations, monitoring and diagnosis of the secondary loop of process layer is an important part. However, nowadays there is no effective means of graphical visualization, and it is often necessary to manually generate them in engineering applications, which results in low maintenance efficiency. In this paper, an automatic diagram generation scheme is provided for process level network and process level signal circuit. The process level network diagram includes the connections between IED devices and switches and the cascading relationships between switches. The automatic diagram generation process includes modelling, generating global layout, generating local layout, and coordinate adjustment of drawing objects. Firstly, the Ethernet switch port will be modelled and incorporated into the SCD of substation. The topological relationship information of process level network can be obtained from SCD. Secondly the hierarchical tree structure is adopted to generate a global hierarchical layout of “Switch - Switch” and a local layout of “Switch - Connected IED” is generated by e “Double wild-goose type”, “Upper wild-goose type” and “Lower wild-goose type”. Then, according to the size of the graph, the coordinates of the drawing objects and routing are adjusted dynamically. The process level signal circuit diagram includes the signal relationship between IEDs and its middle virtual isolator. The automatic diagram generation process includes defining templates, analyzing models to obtain connection relations, importing templates to generate drawing object and connection, and adjusting the coordinates of drawing objects dynamically. Firstly, the left, middle and right layout and various drawing object shapes are defined according to the usage habits, Secondly the signal connection relationship of the main IED in the screen is obtained from the SCD, and the drawing objects is imported according to the template, then, according to the size of the graph, the coordinates of the drawing objects and the dynamic adjustment of the routing are formed, In the circuit diagram the, selected secondary equipment is taken as the graphic center, and the layout on both sides is uniform according to the number of virtual terminals. Through the above methods, the process level network diagram and signal circuit diagram can be drawn with “One-click”. The method proposed in this paper has been applied in the process level network monitoring system of smart substation. It provides an automatic diagram generation function for the drawing software. The automatically generated graph conforms to the user's habits, and is simple and clear, which is convenient for operation monitoring and network failure location. The practice shows that the method proposed in this paper can realize the visualization of process level network diagram and signal circuit diagram without manual drawing, and the maintenance efficiency of the project is greatly improved.

The method of the parametric synthesis of electrical devices circuit diagrams implemented on the basis of the strict inverse statement of the analysis problem is described in the paper. In this case, the input and output parameters of the device circuit diagram must be specified in accordance with the technical design assignment or can be defined from the equations of state on the basis of solving the direct problem. With the purpose of solving the inverse problem, that is, finding the diagram components parameters on the basis of the available information on the state variables vector and the input actions vector, the equation of state is used. The problem solving by the example of the series resonant inverter is presented, from which it follows that the parametric synthesis problem solution obtained on the basis of the suggested method is accurate. The conclusion is drawn that the unified methodology of the electrical devices parametric synthesis on the basis of the equations of state based on the strict inverse statement of the analysis problem is possible.

The paper presents the circuit diagram and the parameters of the cross-section for the model of the power supply (PS) bus of a spacecraft. The optimization of the duration of an ultrashort pulse (USP) exiting the PS bus was made by genetic algorithm (GA) for minimizing the voltage maximum along the PS bus. The GA optimization was run 10 times with every set of chromosomes and populations. The graphs of results convergence are presented for every set of GA parameters. The results of these investigations may be useful for estimating the worst case of USP excitation.

This paper is considered the results of comparing the experimental characteristics of a broadband voltage-controlled oscillator (VCO) with the analysis results. This microstrip VCO is implemented in hybrid technology and has a tuning octave range from 6 GHz to 12 GHz. The measured characteristics of a prototype VCO were compared with the results of modeling carried out both in AXIEM, Analyst electromagnetic simulation (EM) simulators and in the Microwave Office (MWO) circuit schematic simulation environment. It is shown that the smallest discrepancy between the measurement results and the calculated data (for the output frequency value - not more than 0.1 GHz) is ensured by the use of the AXIEM EM-simulator.

This paper covers the aspects of the design of microcontroller-based analog-digital control systems for industrial plants. The main stages of the microprocessor control system (MCS) design are considered and sample MCS circuit diagrams are provided. Recommendations are given for the development of discrete mathematical models of control systems.

The article presents a multimotor electric drive system of a roadheader. We made a computer model in the MatLab suite using a Simulink block library and the SimPowerSystems application. An AM-75 roadheader was chosen for the study. We provided a description of the circuit diagram of the primary electric equipment of the roadheader that includes motors of the boom-type implement, rotating flight conveyor, and the picker with two pallet handles. Additional parameters of asynchronous motors, such as active resistances and inductances of the stator and rotor winding, inductive coupling, reduced power, rated current, and structural and winding factors of motors were calculated for the modeling purposes using the Mathcad software. We developed a computer model of direct start of all the asynchronous motors with a production process-based interconnection. Modeling results are presented as time graphs of the primary motor parameters: angular frequency of revolution and electromagnetic torque. We obtained mains voltage and current graphs, as well as an active power consumption graph. The obtained results were qualitatively assessed by determining the relative error of the modeled parameters and the calculated data. In the process of evaluation and analysis of the modeling results, we identified insignificant errors in motor parameters. This indicates a faithful realization of the computer model and a possibility of using it for engineering calculations.

The article describes a bio-inspired approach to the structural and parametric design of microwave circuits based on a genetic algorithm (GA), which permits algorithmic environment in the field of genetic search for solving NP complete problems, in particular, structural-parametric synthesis of a microwave amplifier. The article is aimed at finding ways of structure-parametric synthesis of microwave modules based on a bio-inspired theory. Scientific novelty of the research lies in the development of a modified genetic algorithm for a bio-inspired automated structural and parametric synthesis of microwave modules. The problem statement in the paper is as follows: to optimize the synthesis of passive and active microwave circuits by using a modified GA. The fundamental distinction of a new approach from the known is the use of new modified genetic structures in bio-inspired automatic structural and parametric synthesis, moreover, a new method for calculating a microwave amplifier based on modified GA is presented in the work. Thus, the problem of creating methods, algorithms and software for automated structural synthesis of microwave modules is currently of special actuality. The solution of the problem will improve the quality characteristics of the designed devices; reduce the time and cost of design and lower the requirements for implementation qualifications.

This work proposes a novel master-slave latch D-type Flip-Flop. It consists of a reset-set slave latch and an asymmetrical single data input master latch. By reducing the number of stages and removing signal conditioning circuitry in the master latch, setup time has been significantly reduced and power consumption has improved. The proposed flip-flop is competitive to other state of the art low power flip-flops in addition to the conventional Transmission Gate Flip-flop (TGFF) in terms of performance, power consumption and area. In simulations, the proposed flip-flop has achieved up to 71.5% improvement in setup time, 36.5% improvement in D-Q delay time and up to 56.5% less power delay product (PDP) with 10% data activity compared to Topologically Compressed Flip-Flop (TCFF), which is a low power flip-flop. Further, it has achieved 11% smaller circuit area compared with TGFF. This work includes the proposed flip-flop's circuit schematic, layout design and simulations using Hspice tool with 28nm CMOS technology and a 1V supply voltage at 1 GHz clock (CLK).

This paper illustrates a project work which approaches the design of a power generating system that will utilize the speed of a train. The circuit diagram of the project work has been first drawn on Fritzing based on the proposed idea and the whole system hardware is designed. The successful generated output power is displayed on LCD display. In the proposed model, A SD card has been used whose function is to store the generated parameters at a certain time interval. The prime aim of the aforementioned project is to fulfill the requirements of electrical appliances like fan, bulb etc. on a train coach using the generated power. To employ the kinetic energy of the air to generate power by implementing suitable arrangements in train is the goal of the considered project. The success of the project depicts that the implementation of this technology will certainly help in reducing the consumption of fossil fuels and thus contributes positively in terms of global warming.

One of the key features of most document image digitisation systems is the capability of discerning between the main components of the printed representation at hand. In the case of engineering drawings, such as circuit diagrams, telephone exchanges or process diagrams, the three main shapes to be localised are the symbols, text and connectors. While most of the state of the art devotes to top-down recognition approaches which attempt to recognise these shapes based on their features and attributes, less work has been devoted to localising the actual pixels that constitute each shape, mostly because of the difficulty in obtaining a reliable source of training samples to classify each pixel individually. In this work, we present a convolutional neural network (CNN) capable of classifying each pixel, using a type of complex engineering drawings known as Piping and Instrumentation Diagram (P&ID) as a case study. To obtain the training patches, we have used a semi-automated heuristics-based tool which is capable of accurately detecting and producing the symbol, text and connector layers of a particular P&ID standard in a considerable amount of time (given the need of human interaction). Experimental validation shows that the CNN is capable of obtaining these three layers in a reduced time, with the pixel window size used to generate the training samples having a strong influence on the recognition rate achieved for the different shapes. Furthermore, we compare the average run time that both the heuristics-tool and the CNN need in order to produce the three layers for a single diagram, indicating future directions to increase accuracy for the CNN without compromising the speed.

In digital terminology, a device that compares two numbers which are represented in binary format and determines whether one of the two inputs are lesser than or equal to or greater than the other input is called a comparator. Comparators are generally used in Central Processing units (CPUs) and microcontrollers. In this project, a 2-bit magnitude comparator is designed with 18nm FinFET technology. FinFET technology is used to overcome the drawbacks associated with CMOS technology like channel length, power consumption, delay and area of transistors, etc. The proposing magnitude comparator is compared with the existing CMOS comparator in terms of power and delay. Schematic circuit diagrams of greater than, equal to and lesser than circuits have been simulated using the Cadence Virtuoso tool. Power and delay values are calculated and plotted for different values of supply voltage ranging from 0.1v-1.0v. LVT (Low Voltage) and HVT (High Voltage) analysis are performed separately. FinFET comparators can be used where a fast switching rate is required, to improve the efficiency of control devices and to make devices compact.

In order to realize the hardware universal design of key matrix, function software custom settings and the number of keys can be expanded in the human-computer interaction scenario. The OLED display technology are studied, and the key matrix based on OLED display technology is designed. According to study the driving principle of OLED display keys, the circuit schematic diagram of LPC1788 controller, realizes the configurability of the software for displaying text and pictures. The key matrix design based on OLED display technology is stable, reliable, clear, versatile, beautiful in appearance, friendly in man-machine interface, and can be widely used in man-machine interaction system for keyboard requirements of vehicle, ship and airborne.

The paper presents development of a circuit solution and a primary detector of a capacitive pressure sensor. Various structural variants of pressure sensors are considered, their characteristics are discussed. Operational principle and structure of the developed primary pressure detector are described, its schematic circuit diagram is presented. The dependency of output signal from the press force is empirically obtained, exhibiting a linear pattern. The estimated value of cyclic drift of the prototype device makes up 0.48% for the upper loading values and 1.08% for the lower ones, by respective weights of 10.69 and 29.03 N. The output signal of the experimental sample is close to linear in the load range from 0 to 8 N, and linear in the range from 8 to 50 N. The sensitivity of the prototype device to the applied pressure is 0.072 V/N. The developed sensor is applied in the feet of a walking robot to determine the zero moment point and calculation of pressure application point on foot.

The work is devoted to the efficiency evaluation research for the capillary mats application in the heating and cooling systems at workshops and data centers of industrial enterprises. The work performs the calculation of the heat load and the design of heating and cooling systems of industrial enterprises and the analysis of the proposed circuit diagrams Based on the calculations performed, the necessary equipment was selected for the heating and cooling systems operation at the enterprises and the economic effectiveness of the system was revealed. The payback period was determined as 5 years.

In nano-technology, Quantum dot is a new technology that has recently become one among the most prominent research areas that has the caliber of getting applied in construction of computers in near future. This paper includes additional features of achieving easiness in processing, deriving the features, compressing and storing the discrete images using reversible logic technique in Quantum dot Cellular Automata, over the translation of color space method. Additionally, we are employing the method of aggregation of color stream. The complete circuit is implemented in Quantum Dot Cellular Automata to reduce power dissipation and cell area. Further analysis has been done for delay and simulation time of each of the computing elements involved in the development of architecture of reversible full summer. The standard full summer is a core aspect of the design of aggregation of color stream architecture. This paper focuses on development of new logical circuits for some of the reversible gates that are needed to build a reversible summer. The designs that are being proposed in this paper are very unique, novel and efficient with its associated output waveforms. By using reversible gates, an effective reversible summer can be developed whose circuit diagram is discussed in the lower section. It is a well-known fact that reversible logic can be deployed to reduce the power dissipation and cell area, hence modelling and simulation has been done with reversible logic in QCA Designer. It has been observed that cell area of each computing element in the full summer is approximately 0.05µm2 which is very less and will ultimately lead to design of low power VLSI for fabrication. Also, it has been noticed that the average simulation time is 1000ms. This can be applicable in biomedical field to allow real time tissue imaging(bio-imaging), diagnosis, single molecule samples, and drug delivery among many otherfields.

The structure of a digital pulse coherent NQR spectrometer with a minimum number of functional units for the investigation of GaSe and InSe layered semiconductor crystals is proposed. The feature of the proposed measuring setup is the implementation of all algorithms of digital processing and signal synthesis in the basis of one statically-configured FPGA EP4CE15E22C8. The digital 48-bit frequency synthesizer provides the formation of carrier frequency oscillations, which fill of the excitation pulses in the NQR frequencies range 1 –50 MHz (isotopes 14N, 69Ga, 71Ga, 113In, 115In, and others). Reliable gating of the receiver in the pauses between the excitation pulses (up to 100 dB for the carrier frequency) is ensured by a circuit diagram of three stages of the same type on double gate field-effect transistors.

Detection of circuit components from handdrawn circuit image refers to the process of automatic separation of all the circuit components belonging to a circuit. In this work, we have devised an algorithm that accepts a hand-drawn circuit image as input and returns the circuit components marked with bounding box. We have proposed a method where we have used the morphological ‘close’ operator to create a structural dissimilarity between the circuit components and the wires. Then we have used run length smoothing algorithm (RLSA) based technique to remove all the wires. Finally, we have used the spatial coordinates of the circuit components in the wire-removed circuit diagram to localize them in the actual circuit diagram. The proposed methodology is evaluated over a database consisting of 60 circuit images collected from the copies of engineering students. Considering the complexity of the research topic, the result thus obtained is encouraging.

Iontophoresis is increasingly being used to treat purulent wounds and maintain skin tone. However, for highly effective treatment, a sufficiently frequent repetition of this procedure is required. Therefore, it was decided to try to develop a portable device for iontophoresis. To establish acceptable parameters, a chemical review of the processes occurring during iontophoresis was conducted. Based on a chemical review and analysis of existing analogues, a portable device for iontophoresis in the form of a patch was developed. The article describes the main stages of development (selection of components, substantiation of the circuit diagram, etc.) and reviews the chemical assessment of the effectiveness of iontophoresis.

In this paper, we introduce a current sensing scheme for on-chip power management. The proposed scheme uses the voltage drop across the MOSFET switch in a DC-DC converter for sensing the current and a time-domain circuitry for digitization. Minimal use of analog circuitry in the architecture not only reduces the power consumption but also makes the design simple to realize. The scheme offers tolerance against variations in process and temperature by comparing the sensed voltage against a reference voltage that is reflective of the amount of variation present. Proposed circuit schematic was designed and simulated using 55nm CMOS technology alongside a switching regulator. The simulated circuit could measure currents up to 600mA with a maximum measurement error of only +/−2.5%. The proposed scheme could measure current within a measurement time of 2uS while consuming only 200uA from a 1.8V supply.

This paper proposes a reduction of DC-link voltage fluctuation for hydraulic turbine generation (HTG) systems using back-to-back (BTB) converters. In HTG systems, a BTB converters with two-level topology have been mainly used. Because of its strong points of being intuitive in circuit diagram and easy to maintain. A switch-open-fault in the grid-stage converter of the BTB converter causes the fluctuation of DC-link voltage in the BTB converters. It reduces the reliability of the HTG systems. To improve the performance of the HTG systems generally, supplementary circuits or components and tolerant control methods are required. Therefore, this paper proposed method to reduce the fluctuation of DC-link voltage when switch-open-fault is happened in the grid-stage converter. The validity of the proposed method to reduce the fluctuation of DC-link voltage is substantiated by simulation results.

In power electronics, wide band gap materials enable faster transients and higher switching frequencies. Therefore, more efficient power electronic systems can be realized, but also greater EMC problems in magnitude and frequency arise. Heat sinks, which are often necessary for cooling power semiconductors, are a well known source of EMC issues. In this paper, crucial sources of conducted interference from capacitive coupling via the heat sink are determined and approaches to reduce this conducted interference are discussed. For the investigations, a combined approach using simulation as well as circuit diagram analysis was used. Three different topologies were investigated to obtain general recommendations to reduce interference caused by heat sink capacitive coupling.

Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this work, two logic encrypted full adder and subtractor circuits and half adder and half subtractor circuits using logic encrypted gates are designed and proposed. Of the two proposed circuits for adders and subtractors, one is strong logic encrypted than the other. All the encrypted adders and subtractors are compared with conventional adders and subtractors for logic encryption level and various other parameters like area and power. The results show improvement in area and power. The proposed half adder has 42% more area and 26.02% more power and half subtractor has 50% more area and 24.4% more power than the existing circuits. The proposed full adder has 25% less area (transistor count) and 33% less power consumption and the proposed full subtractor is also better in terms of area and power consumption with 30% and 24% lesser. Even strong logic encrypted full adder and full subtractor are proposed in this work. Full adder and subtractor have 22% increase in area each and on an average 2.3% increase in power each respectively.

A physical model representing an underdamped free oscillation of a cantilever beam is constructed. The model is incorporated into a pSPICE Analog Behavioral Model (ABM) in order to construct a circuit schematic that generates a model-based waveform representing that of the experiment. A strain gage is employed to sense the change in strain in the oscillating cantilever beam. The frequency and damping ratio of oscillation of the cantilever are determined by means of curve fitting. Experiment and pSPICE ABM results show an excellent agreement.

Electroporation is a process that uses a high voltage pulsed electric field to permeate the cell membrane for drug infusion into the cell. Changing the voltage level, pulse period or pulse width modifies the effect of the treatment to the cell. In this paper, we describe a miniaturized high-power pulsed electric field generator that reduces the system to a single chip. The proposed chip allows various customizations in terms of frequency or duty cycle of the applied pulse. The circuit is designed in 1 μm silicon-on-insulator CMOS process, named XDH, from X-FAB. The circuit schematic simulation showed a duty cycle variation from 12.5% to 34.9% and can generate 465 kHz, 500 V square wave.

CISPR 32[1]specifies several types of asymmetric artificial network (AAN) for conducted emission measurement on unscreened balanced pair cables. The AAN circuit diagram shown in Figure G.3 of CISPR 32[1]is an example of a transformer-type-AAN, thought to be suitable for measurement on single, two, three and four unscreened balanced pairs even though EUT port of the AAN is a balanced four-pair connector. In this paper, we explain how we experimentally verified the suitability of this transformer-type-AAN by measuring common mode termination impedance and voltage division factor (VDF) while changing the balanced pairs to be measured. The results show that deviations among the measured values were sufficiently small and all measured values were met the requirements of CISPR 16-1-2[2]. We concluded that this transformer-type-AAN is suitable for conducted emission measurement on any unscreened balanced pairs.

This paper presents a method for finding the optimum load resistance that maximizes the power efficiency of a tuned-resonant inductive power transfer (IPT) system. In this method, the equivalent AC circuit of the IPT system is transformed to match the topology of a reference ladder prototype. This simplifies the design problem, because the ladder prototype offers intuitive and accurate closed-form approximations for the optimum load resistance and maximum power efficiency. The process is graphical in the sense that manipulations and transformations are made directly on the circuit diagram. Compared to traditional circuit analysis, the ladder prototype approach does not entail complicated systems of equations or matrix manipulations. We show the utility of our method by designing a practical IPT system.

Magnetic-coupled wireless power transfer technology is widely used in wireless charging for electric vehicles (EVs). In this paper, we establish a circuit diagram and a simulation model of WPT charging system for EVs. The magnetic fields from different sights and the E-field strength when the wireless power transmission system is working are simulated and judged by comparing with International Committee on Non-Ionizing Radiation Protection (ICNIRP) guidelines. The current and the voltage of the transmitter coil and receiver coil are given in this paper. Power grid harmonic is also evaluated as the working frequency is offset.

In the IoT for multi-sensor node application [1], there are demanded both high-performance for computation in an active mode, and an ultra-low standby power in a sleep mode for longtime buttery life in the energy efficient system. Ultra-low standby MCU with embedded NVM using 90 nm CMOS technology is also reported [2], but its SRAM cache is not sufficient for applying imaging processing which requires large memory capacity with imaging sensors in edge computing. Embedded SRAMs can be achieved fast read/write access within a few nanoseconds, but consume standby leakage power for data retention, being dominant power in the sleep mode. To reduce the standby leakage power of embedded SRAMs, the source bias design technique with power-gating is introduced on a bulk CMOS device [3]. In the resume standby (RS) mode, the VSS source bias control for SRAM array is demonstrated as an effective SRAM leakage power reduction. Besides, once the large SRAM array are into the resume standby mode, it takes long time to wake-up again. It is not applicable for high-speed CPU operation. Then, a fast resume standby mode (FRS) for cache memories is proposed to wake-up as much as fast. In that FRS mode, the power supply for SRAM peripheral is cutoff but SRAM array is keeping with a VDD supply. Each standby mode and its circuit diagram are summarized in Fig. 1. Meanwhile, dopant-less channel fully-depleted (FD) silicon-on-insulator (SOI) device is proposed [4]–[6] to improve the performance, power, and area (PPA) of embedded SRAMs. FD-SOI enables to control the back-bias (BB) dynamically under the buried-oxide (BOX) to reduce leakage current and/or to improve performance by applying reverse or forward bias, respectively. Fig. 2 presents the block diagram of BB control scheme for voltage scaling in IoT application with FD-SOI structure [7]–[9]. BBs for NMOS (VBN) and PMOS (VBP) can be applied individually by VBB generator (VBB Gen.) circuit. Four operation modes for smart IoT applications are considered. High-performance, normal, low-power operating modes are introduced, along with the required loads in the system. The sleep mode with SRAM data retention for long-term waiting in the sensor nodes is also proposed. Each supply voltage and BB is also shown in Fig. 2. The comparison of embedded SRAM leakage power is shown in Fig. 3.

DC-AC conversion with three phase single ended primary inductance inverter and boost converter is a advanced design when comparing with conventional topologies .Here only used four-switches and three-phase SEPIC inverter .This pro- posed inverter is designed to reduce the fare, difficulty and switching losses .Converter offer a design for the inverter with the combination of single-ended primary-inductance with DC- DC converter which can be upgrade the phase voltage than traditional FSTP single ended primary inductance inverter . For boost up the output voltage inserting a boost converter (DC-DC) between input side and the four switch three phase single-ended primary-inductance inverter . Constant current control strategy is used with the proposed topology . Working principle , circuit diagram and simulation diagrams also introducing in this paper .

Circuitry solution has been developed to create a prototype of the system for the registration of the high frequency human skin temperature oscillations. As they connected with blood circulation, such method allowing in the future to provide the registration of the pulse wave signal, for measuring heart rate in portable devices like smart watches and fitness bracelets. The miniature semiconductor chip diodes sensor has been used. The electronic system for the calibration of the device has been designed. For providing operation of the system in a full voltage range using the automatic set has been used for the maintenance of the operating point and of the necessary slope of the conversion factor (Volts / °C). The structural and circuit diagram has been developed. They consisted of two parts: the remoted preamplifier with the temperature sensor and the main block including all the other digital and analog parts. The developed system has following technical characteristics: the temperature resolution to be 0.01 °C and the thermal time constant of the sensor 0.05 s. The registration system testing has been performed in two ways: in a thermostat and on the human skin surface. Device contains plethysmo- and ECG-channels for obtaining data on the phases of cardiac cycles and synchronous analysis of physiological processes. The cross correlation coefficient between the temperature oscillations and the pulse wave signals laid in the diapason from 0.53 to 0.65.

The article covers a study of dynamic behavior of a vibration protection system with a controlled stiffener represented by a linear DC motor (LDCM). It also considers a dual-mass oscillation system with parallel layout of stiffeners and viscous friction elements (Kelvin circuit diagram). With due regard to the assumptions made, the authors have obtained mathematical models represented by transfer functions. In the disturbances channel, the models obtained for the input and output variables were represented by the mount acceleration, and the protected object acceleration, respectively; in the control channel, the models obtained for the input and output variables were represented by the extended force impact coming from the LDCM, and the protected object acceleration, respectively. A design of a closed-loop vibration protection system aimed at vibrational acceleration of the protected object was developed. Based on a simulation model complying with the obtained mathematical models, the authors have analyzed the efficiency of the developed system with integral and proportional plus integral control law controllers. Using the obtained data on system efficiency, the authors have defined recommendations for use of the said controllers in a vibration protection system with LDCM.

The structure and organization of the data transmission system for a distributed real-time information-control system are considered in this paper. The fault-tolerant structures of the local network combining packets switching and channels switching methods are proposed. Original circuit diagrams of transceivers based on a current loop with using feedback for error detection are developed.