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Traditionally, Dow ell's one-dimensional method is used to calculate the AC winding loss factor for transformers with reasonable accuracy in most cases. However, for thin film transformers there can be significant two-dimensional fields which, if ignored will lead to erroneous results. The problem is exacerbated for transformers used in Flyback DC-DC converters which are exposed to arbitrary current waveforms. In this paper we derive the resistance matrix for a closed core transformer accounting for the two-dimensional fields present. The derived resistance matrix can then be used to analytically calculate AC winding loss for arbitrary current waveforms such as those found in Flyback converters.

With the advent of PwrSoC/PwrSiP systems comes a wide range of process variables which the designer is required to optimize. However, as the number of parameters increases, so too does the complexity of the design. If active and passive components are not optimized in unison the advantages these highly integrated systems bring are negated. Considering this, the need for an intuitive design tool for the practicing engineer to quickly analyze a range of potential system configurations and find the Pareto optimal design with ease is clear. In this paper we present a new Electronic Design Automation (EDA) package, the Ferrochip Design Studio for the co-optimization of DC-DC converter systems, primarily for PwrSoC and PwrSiP systems using thin film integrated magnetics. We discuss its constituent parts as well as presenting the design flow used by the tool. Finally small signal measurement results are presented and compared to the analytical results generated by the design studio.

The application of coupled vs. non-coupled inductors in a phase-interleaved PV boost module-integrated-(MIC) converter is investigated in terms of inductor size, output voltage ripple and circuit efficiency. Reduced circuit size is the main motivation in this case whereby inductors currently dominate MIC size. Interleaved inductors provide one step towards size reduction by enabling current ripple cancellation at the converter input and output, so that the size of capacitors is significantly reduced. Further reduction in inductor size is demonstrated through the application of coupled inductors, in which two-phase inductors share the same core, to provide the same effective inductance as two larger non-coupled phase inductors.

Currently there is a great interest in inductors-on-silicon for power-supply-on-chip applications (PwrSoC), with an ultimate goal of integrating passive and active components on a single silicon die to reduce power supply size. While power levels of individual circuits are low, there is an ever-increasing trend towards ubiquitous computing; with the result that power consumption of mobile computing accumulates to a significant load demand from the grid. Inductor-on-silicon research to date has focused on optimising technologies for maximum power density and efficiency, without considering particular inductor specifications. In this paper a method for designing inductors-on-silicon based on a given DC-DC converter specification is presented.

Recently a great deal of work has been done to improve the efficiency of DC-DC converters at light-load. This has been driven by the desire to increase battery life in portable devices and to reduce standby power consumption in mains powered devices. In general, power supplies are moving towards higher switching frequencies to reduce passive component size, resulting in higher switching and gate drive power loss. Several methods to reduce power loss at light-load including Pulse Frequency Modulation and Diode Emulation are investigated in this paper. These methods however result in higher inductor current ripple as the inductor is designed for operation when output current is at its maximum. Distributing inductors in parallel is shown to provide a means for increasing the effective inductance at light-load through reducing current ripple.