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Hardware faults (i.e., soft errors) are projected to increase in modern HPC systems. The faults often lead to error propagation in programs and result in silent data corruptions (SDCs), seriously compromising system reliability. Selective instruction duplication, a widely used software-based error detector, has been shown to be effective in detecting SDCs with low performance overhead. In the past, researchers have relied on compiler intermediate representation (IR) for program reliability analysis and code transformation in selective instruction duplication. However, they assumed that the IR-based analysis and protection are representative under realistic fault models (i.e., faults originated at lower hardware layers). Unfortunately, the assumptions have not been fully validated, leading to questions about the accuracy and efficiency of the protection since IR is a higher level of abstraction and far away from hardware layers. In this paper, we verify the assumption by injecting realistic hardware faults to programs that are guided and protected by IR-based selective instruction duplication. We find that the protection yields high SDC coverage with low performance overhead even under realistic fault models, albeit a small amount of such faults escaping the detector. Our observations confirm that IR-based selective instruction duplication is a cost-effective method to protect programs from soft errors.

A local bundle adjustment is an important proce- dure to improve the accuracy of a visual odometry solution. However, it is computationally very expensive as it jointly optimize all the poses of cameras and locations of map points. To reduce the computational complexity of a local bundle adjustment, the state-of-the-art algorithms [1]–[3] were proposed to manipulate the map point variables, using extra matrix operations, from their linearized optimization solutions. Instead of relying on complex matrix manipulations, this paper proposes a novel way of addressing this complexity issue-we represent a map point as a function of two camera poses, and uses the triangulated location of the map point when needed. Our method is more efficient than ones in the full-SLAM formulation in solving the visual odometry problem in that 1) the complexity of our solution is lower than those of the state-of-the-art methods, 2) no extra matrix operations required to eliminate map points, 3) no need guesses on map points' initial locations. Experiemental results, through simulated experiments and experiments with the KITTI dataset, demonstrated that our results are more accurate than those of a full-SLAM approach with lower runtime complexities.

Single bit-flip has been the most popular error model for resilience studies with fault injection. We use RTL gate-level fault injection to show that this model fails to cover many realistic hardware faults. Specifically, single-event transients from combinational logic and single-event upsets in pipeline latches can lead to complex multi-bit errors at the architecture level. However, although accurate, RTL simulation is too slow to evaluate application-level resilience. To strike a balance between model accuracy and injection speed, we refine the concept of hierarchical injection to prune faults with known outcomes, saving 62% of program runs at 2% margin of error on average across 9 benchmark programs. Our implementation of the hierarchical error injector is not only accurate but also fast because it is able to source realistic error patterns using on demand RTL gate-level fault injection. Our tool outperforms state-of-the-art assembly-level and compiler-based error injectors by up to 6X, while providing higher fidelity.

Memory system performance is measured by access latency and bandwidth, and DRAM access parallelism critically impacts for both. To improve DRAM parallelism, previous research focused on increasing the number of effective banks by sub-dividing one physical bank. We find that without avoiding conflicts on the shared resources among (sub)banks, the benefits are limited. We propose mechanisms for efficient DRAM resource utilization and resource-conflict avoidance (ERUCA). ERUCA reduces conflicts on shared (sub)bank resources utilizing row address locality between sub-banks and improving the DRAM chip-level data bus. Area overhead for ERUCA is kept near zero with a unique implementation that exploits under-utilized resources available in commercial DRAM chips. Overall ERUCA provides 15% speedup while incurring

This study proposes a single-inductor bipolar multiple-output (SIBMO) boost converter utilizing pulse frequency (PFM) control for organic light-emitting diode (OLED) drivers and optical transducers. The purpose of the converter designed herein is to provide multiple voltage sources with opposite polarities to meet the requirements of various applications such as OLEDs or optical transducers. The bipolar voltage sources are essential for offering alternating driving voltages to extend the lifetime of OLEDs. The converter boosts the input of 2.8 V to two positive and two negative outputs, i.e., +12 V, +6 V, −12 V, and −6 V. Different from the commonly-used pulse width modulation (PWM), the constant on-time (COT) approach is adopted herein with a dynamic charging algorithm to automatically adjust the operating frequency, thus profiting from less circuit complexity, improvement of cross regulation, and high transfer efficiency in unbalanced load cases. The total maximum output power is 320 mW, as the switching frequency varies from 650 kHz to 0 Hz, and the maximum efficiency reaches 83.1% by simulation. The converter was fabricated by TSMC 0.25μm 1P3M high voltage CMOS technology for verification.

A constant on-time (COT) single-inductor bipolar multiple-output (SIBMO) on-chip boost converter is proposed for LCD drivers in this study. The converter is designed for biasing some analog and digital circuits fabricated on glass substrates for benefits of extending the life of LCD. These circuits on glass require bipolar high voltages for drive LCDs. The converter boosts the input of 2.8V to two positive outputs and two negative outputs, +12V, +6V, −12V and −6V, respectively. Different from the commonly-used pulse width modulation (PWM), the constant on-time (COT) is adopted herein by a dynamic charging algorithm whose frequency is adapted to the varied output voltage level, thus enjoying the merit of less circuit complexity and a smaller chip area. The COT is in this study further developed to a ripple-based one for achieving applicability even with unbalanced output loads with high efficiency. While total maximum output power is 260mw and the switching frequency varies from 500 kHz to 650 kHz, the maximum efficiency reaches 82.4%. The converter is fabricated by TSMC 0.25μm 1P3M high voltage CMOS technology for verification.

A new rectifier (AC-DC) charge pump with impedance matching is proposed in this study for maximizing power transfer efficiency in an energy harvester circuitry equipping self-powered sensors. In addition to the rectifier charge pump, there are power management circuits, a low dropout regulator and a battery charger to complete the energy harvester circuitry module for self-power sensors. The proposed circuit is suitable for harvesting the low-frequency vibration energy in portable medical sensors or low-power high-frequency RFID sensors. In the harvester circuit, the rectifier charge pump operated in dual phase is proposed to preform efficient conversion of vibratory AC powers to DC by means of automatic switchings and capacitors. To optimize the charge pump circuit, a charging equivalent model is first derived, where all capacitances are optimized to derive maximum average energy stored in capacitors and then transferred to loadings. The design rules are distilled based on rigorous analysis, and the capacitances are optimized based on the relation between the energy stored in capacitances and inherent electronic properties of the harvester. The chips with optimized capacitances are fabricated by the TSMC 0.35um process for verification. It is shown theoretically and experimentally that implementation of the proposed optimized circuit is able to harvest more power than un-optimized.

Given two sets of videos captured by two sets of multiple cameras, we like to combine them to create a new stereo scene with the foreground objects from one set of video and the background from the other set. We address the camera parameter mismatch and camera orientation mismatch problems in this paper. We propose a floor model to adjust the camera orientation. Once we pick up the landing point (of foreground) in the background scene, we need to adjust the background camera parameters (position etc.) to match the foreground object. The depth information is needed in the above calculation. Thus, new background scenes may have to be synthesized based on the calculated virtual camera parameters and the given background pictures. Plausible results are demonstrated using the proposed algorithms.

Over the past few years, Vehicular Ad Hoc Network (V ANETs) has gained much attention. In V ANETs, the rapid movement of vehicles lead to the frequently handoff in different access points or base stations. To ensure that the transmission of packets will not be interrupted, how to reduce the delay of handoff is an important design issue. In view of this, we proposed a fast handoff scheme, called AAFHS. When vehicles leave the communication range of an access point (AP), their IP addresses can be reserved in the AP. Then the AP can pass the reserved IP addresses to the vehicles that are going to enter the communication range of the AP. In this way, it can reduce the use of DHCP to obtain IP addresses. Our simulation results show that the proposed fast handoff scheme can be used to effectively reduce the handoff time.