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Electronic noses (e-nose) have been studied for several years and extensively applied; however, they are limited by their volume and high manufacturing cost. Portable devices have become popular in recent years; therefore, it is crucial to integrate e-noses in portable devices (e.g., mobile phones). This study used TSMC 90nm 1P9M CMOS MSG technology to develop a front-end system-on-chip (SoC) for an electronic nose. The SoC contained interdigitated electrodes, multi-channel sensor interface circuits, an analog to digital converter, and a digital continuous restricted Boltzmann machine (CRBM). Various conducting-polymer materials were titrated on the interdigitated electrodes to form an on-chip sensor array. This SoC was controlled through an external microcontroller to perform odor identification and analysis. The simulation results of the SoC and gas classification show that this chip is suitable for portable applications and further integration.

This work describes a novel triple-band bio-telemetry system that is implemented using a miniaturized implantable antenna and triple-band communication circuits for implantable applications. The proposed miniaturized implantable antenna effectively covers three bands for 402 MHz at MICS (medical implant communications service) band, 433 MHz and 2.4 GHz at ISM (industrial, scientific, and medical) band by using radiator of π-shape with stacked and spiral structure. This triple-band communication circuits consist of a 402 MHz data transmission telemetry and a 433 MHz wireless powering transmission circuit, as well as a 2.4 GHz wake-up controller circuit. The system was successively integrated and could substantially improve the life-time of the implantable device.

An ultra wide-range delay-locked loop (DLL) has been fabricated in 65nm CMOS technology. The proposed leakage delay unit (LDU) can easily generate a large propagation delay to reduce the difficulties to build up the high-speed digital counter in the cycle-controlled delay unit (CCDU) for a very low-frequency operation. The proposed DLL circuit can operate from 500 KHz to 1 GHz, and the power consumption is 1.8mW @1GHz with very small active area (0.01mm2).

Neural prosthesis is a promising technique to enable paralyzed patients with conditions, such as spinal cord injury or spina bifida (SB), to control their limbs independently. However, it remains unknown whether muscle activity detected from paralyzed patients can be used to predict and reproduce their altered gait patterns that can be employed to provide closed-loop feedback for neural prostheses. In this study, we recorded muscle activity of people with SB during overground walking and developed a Self-Organizing Adaptive Prediction (SOAP) technique for neural prostheses. This technique can provide 80% more accurate prediction of end-point impaired locomotion for people with SB compared to traditional robust regression. Our results suggest that control of complex neural prostheses during locomotion can be achieved by engaging muscle activity as intrinsic feedback to generate end-point leg movement.

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die- level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

This paper describes a novel Uniform-Channel-Program-Erase (UCPE) flash EEPROM technology using an isolated P-well structure for high performance and low power applications. The UCPE bit cell utilizes Fowler-Nordheim (FN) tunneling in the channel region for both program and erase operations. By implementing a 0.55 /spl mu/m trench isolation and a triple well process, an experimental UCPE bit cell has been demonstrated in a 0.18 /spl mu/m technology.