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In recent years, as the progress of VLSI technology, artificial intelligence / deep learning has become a major trend. To satisfy the demand of high performance computing, many AI ASICs adopt multi-core architecture. The challenges for clocking of this architecture consists of timing closure issues and the implementation of low latency, low skew and low OCV top-level clock tree for highspeed operation (> 1GHz). In this paper, we share our experiences on clock tree synthesis of HPC ASICs. Two different clocking strategies are introduced including H-tree planning with customized big drivers and clock mesh.

We present our experience of DFM (design for manufacturability) and DFY (design for yield) considerations on physical designs at 0.13 mum and below technology nodes. The impact of some DFM approaches on timing and signal integrity are addressed. We also present our experience of yield analysis and improvement for the designs with process variation and dynamic IR drop issues.