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The identification of grape leaf diseases based on deep learning is critical to controlling the spread of diseases and ensuring the healthy development of the grape industry. Focusing on the lack of training images of grape leaf diseases, this paper proposes a novel model named Leaf GAN, which is based on generative adversarial networks (GANs), to generate images of four different grape leaf diseases for training identification models. A generator model with degressive channels is first designed to generate grape leaf disease images; then, the dense connectivity strategy and instance normalization are fused into an efficient discriminator to identify real and fake disease images by utilizing their excellent feature extraction capability on grape leaf lesions. Finally, the deep regret gradient penalty method is applied to stabilize the training process of the model. Using a total of 4,062 grape leaf disease images, the Leaf GAN model ultimately generates 8,124 grape leaf disease images. The generated grape leaf disease images based on Leaf GAN model can obtain better performance than DCGAN and WGAN in terms of the Fréchet inception distance. The experimental results show that the proposed Leaf GAN model generates sufficient grape leaf disease images with prominent lesions, providing a feasible solution for the data augmentation of grape leaf disease images. For the eight prevailing classification models with the expanded dataset, the identification performance based on CNNs indicated higher accuracies, whereby all the accuracies were better than those of the initial dataset with other data augmentation methods. Among them, Xception achieves a recognition accuracy of 98.70% on the testing set. The results demonstrate that the proposed data augmentation method represents a new approach to overcoming the overfitting problem in disease identification and can effectively improve the identification accuracy.

In this paper, we consider the control problem for multiplicative noise system with intermittent noise and input delay. For the finite-horizon case, in virtue of the dynamic programming approach, the optimal output feedback controller is proposed for the first time. For the infinite-horizon case, it is shown that the multiplicative noise system can be stabilized if and only if the given modified Riccati equation has the unique solution.

Lasers with orbital angular momentum (OAM) holds promise for compact, at-source solutions for applications in imaging and communications. In this work, we demonstrate an electrically pumped terahertz vector vortex quantum cascade laser, (THz-VV-QCL) which is fabricated by monolithically integrating a ring resonator with periodic double slits scattering elements, bus waveguide, and a distributed feedback QCL. To compensate for radiation and material losses, the ring resonator is pumped by the metallic air bridge. The mode purities of left/right-circularly polarized light are 87.7%/91%, respectively. The integrated THz-VV-QCL shows the great potential for application in THz communication and image.

Reconfigurable architectures are today experiencing a renewed interest for their ability to provide specialization without sacrificing the capability to adapt to disparate workloads. Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) while offering increased hardware efficiency with respect to field-programmable gate arrays (FPGAs). This makes CGRAs a promising alternative to enable power-/area-efficient acceleration across different application domains. Unfortunately, specializing and implementing a CGRA for a specific application domain requires the exploration in a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc.) and involves enormous software/hardware engineering effort (e.g., modeling, testing, and evaluating the CGRA, map operations onto the CGRA, etc). In this paper, we discuss a hardware/software co-design framework* to automatically specialize and implement optimal CGRA designs given a set of applications of interest.

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units interconnected through a network-on-chip (NoC), provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). Unfortunately, designing a CGRA for a specific application domain involves enormous softwarelhardware engineering effort (e.g., designing the CGRA, map operations onto the CGRA, etc) and requires the exploration on a large design space (e.g., applying appropriate loop transformation on each application, specializing the reconfigurable processing elements of the CGRA, refining the network topology, deciding the size of the data memory, etc). In this paper, we propose AURORA* - a hardware/software codesign framework to automatically synthesize optimal CGRA given a set of applications of interest.

Reconfigurable accelerator fabrics, including coarse-grain reconfigurable arrays (CGRAs), have experienced a resurgence in interest because they allow fast-paced software algorithm development to continue evolving post-fabrication. CGRAs traditionally target regular workloads with data-level parallelism (e.g., neural networks, image processing), but once integrated into an SoC they remain idle and unused for irregular workloads. An emerging trend towards repurposing these idle resources raises important questions for how to efficiently map and execute general-purpose loops which may have irregular memory accesses, irregular control flow, and inter-iteration loop dependencies. Recent work has increasingly leveraged elasticity in CGRAs to mitigate the first two challenges, but elasticity alone does not address inter-iteration loop dependencies which can easily bottleneck overall performance. In this paper, we address all three challenges for irregular loop specialization and propose ultra-elastic CGRAs (UE-CGRAs), a novel elastic CGRA that accelerates true-dependency bottlenecks and saves energy in irregular loops by overcoming traditional VLSI challenges. UE-CGRAs allow configurable fine-grain dynamic voltage and frequency scaling (DVFS) for each of potentially hundreds of tiny processing elements (PEs) in the CGRA, enabling chains of connected PEs to “rest” at lower voltages and frequencies to save energy, while other chains of connected PEs can “sprint” at higher voltages and frequencies to accelerate through true-dependency bottlenecks. UE-CGRAs rely on a novel ratiochronous clocking scheme carefully overlaid on the inter-PE elastic interconnect to enable low-latency crossings while remaining fully verifiable with commercial static timing analysis tools. We present the UE-CGRA analytical model, compiler, architectural template, and VLSI circuitry, and we demonstrate how UE-CGRAs can specialize for irregular loops and improve performance ($ 1.42-1.50\times$) or energy efficiency $(1.24-2.32\times)$ with reasonable area overhead compared to traditional inelastic and elastic CGRAs, while also improving performance ($ 1.35-3.38\times$) or energy efficiency (up to $1.53\times$) compared to a RISC-V core.

Due to the popularity of Windows system, BitLocker is widely used as a built-in disk encryption tool. As a commercial application, the design of BitLocker has to consider a capability of disaster recovery, which helps a user to recover data stored on encrypted disk when a regular access is not available. In this case, it will inevitably lead to some security risks when using BitLocker. We have a deep exploration of BitLocker encryption mechanism in this paper. We present the decryption method of encrypted VMK in case of system partition encryption and non-system partition encryption, respectively. VMK is the core key in BitLocker, with which the encrypted partition or the entire disk can be further decrypted. As for security analysis on BitLocker, we firstly make a difficulty analysis of brute force cracking on BitLocker keys, and then we analyze a possible threat caused by key theft. Based on this, we propose a few countermeasures about BitLocker usage. Additionally, we give some suggestions about security enhancement of BitLocker encryption.

In this paper, we give a fast decryption method of Excel document encrypted by RC4 algorithm. Through a detailed analysis of document storage structure and encryption process, we illustrate the inner principle of key generation and data encryption in the block by block manner. We present an efficient way of recovering the intermediate key by using rainbow table attack, which can be directly applied to decrypt the Excel document. The advantage of our method is that the decryption time of one document is no longer affected by the password length and complexity. In our practical test, it has achieved the decryption of Excel encrypted documents in an average of 3 minutes on a common personal computer, which greatly improves decryption efficiency of encrypted documents compared with the current dictionary and brute force attack methods of recovering document password.

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units (e.g., adder, subtractor, multiplier, divider, or larger multi-operation units, but smaller than a general-purpose core) interconnected through a Network-on-Chip, provide higher flexibility than domain-specific ASIC accelerators while offering increased hardware efficiency with respect to fine-grained reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs). The fast evolving fields of machine learning and edge computing, which are seeing a continuous flow of novel algorithms and larger models, make CGRAs ideal architectures to allow domain specialization without losing too much generality. Designing and generating a CGRA, however, still requires to define the type and number of the specific functional units, implement their interconnect and the network topology, and perform the simulation and validation, given a variety of workloads of interest. In this paper, we propose OpenC-GRA *, the first open-source integrated framework that is able to support the full top-to-bottom design flow for specializing and implementing CGRAs: modeling at different abstraction levels (functional level, cycle level, register-transfer level) with compiler support, verification at different granularities (unit testing, integration testing, property-based testing), simulation, generation of synthesizable Verilog, and characterization (area, power, and timing). By using OpenCGRA, it only takes a few hours to build a specialized power- and area-efficient CGRA throughout the entire design flow given a set of applications of interest. OpenCGRA is available online at https://github.com/pnnl/OpenCGRA.

Quantized Neural Networks (QNNs) have drawn tremendous attention since - when compared with Convolution Neural Networks (CNNs) - they often dramatically reduce computation, communication, and storage demands with negligible loss in accuracy. To find an optimal balance between performance and accuracy, developers use different data-widths for different layers and channels. Given this large parameter space, it is challenging to design a QNN accelerator which is generally efficient for various and flexible model configurations. In this paper we propose CQNN, a novel Coarse-Grained Reconfigurable Architecture-based (CGRA) QNN acceleration framework. CQNN has a large number of basic components for binary functions. By programming CQNN at runtime according to the target QNN model, these basic components are integrated to support QNN functions with any data-width and hyperparameter requirements. The result is an optimal QNN for the target model. The framework includes compiler, hardware design, simulator, and RTL generator. Experimental results show CQNNs can complete the inference of AlexNet and VGG-16 within 0.13ms and 2.63ms, respectively. We demonstrate the design on an FPGA platform; however, this is only for showcasing the method: the approach does not rely on any FPGA-specific features and can thus be implemented as ASIC as well.

With regard to the research on financial risk management, Value-at-Risk(VaR) has been widely accepted as a standard approach to financial risk management. There are various ways applicable to calculate VaR, of which Monte Carlo Simulation is regarded as the most effective one to deal with VaR calculation. Nevertheless, the calculation accuracy of the Monte Carlo Simulation method tends to be affected by the scale of simulation. As the scale of simulation increases, the calculation accuracy improves. In the meantime, however, the time cost rises on a continued basis. Therefore, it is difficult for the Monte Carlo Simulation method to be applied in practice. In order to solve this problem, a parallel Monte Carlo Simulation calculation method based on Intel MIC architecture is proposed in this paper to calculate VaR. The simulation process consists of a group of simulation tasks at a time. Due to the absence of data dependency between each simulation task, it is capable of excellent parallelism. In this paper, the OpenMP programming model was applied to assign each simulation task to a different thread for execution. Then, a comparison was performed between the CPU sequential execution scheme, the scheme based on MIC offload mode and the scheme based on MIC native mode. According to the comparative results, the solution based on MIC native mode is superior to that based on MIC offload mode. When the number of times for simulation to be conducted reaches 50,000, the parallel algorithm in MIC native mode achieves a maximum speed-up of 93.2 times compared to CPU sequential calculations, which could make the Monte Carlo Simulation of VaR calculations suitable for practical application.

Electromagnetic spectrum sensing is an important component of electromagnetic spectrum capability. With the development of spectrum sensing technology, there are still many problems and challenges in practical applications. For example, though the spectrum sensing field has diversified, the system is still based on manual operation; there are massive and diverse data, but the depth and breadth of data mining are insufficient; there is a large amount of historical data, multiple heterogeneous and unlabeled data types, and multidimensional non fusion platforms. The above difficulties hinder the construction of electromagnetic spectrum sensing ability and efficiency. Therefore, we propose a spectrum sensing system based on composite neural network architecture, the overall architecture includes three layers; spectrum sensing layer, data processing layer and situation analysis layer, which realizes the bottom data processing and high-dimensional spectrum sensing analysis. With the development of artificial intelligence technology [1], the above problems can be further improved and the development from artificial to intelligent can be realized gradually by using deep learning algorithm framework and exploring the advanced artificial intelligence technology. Finally, a three-dimensional electromagnetic situation map is formed from the time dimension, space dimension and spectrum dimension, so as to realize intelligence.

Return-Oriented Programming (ROP) is a sophisticated exploitation technique that is able to drive target applications to perform arbitrary unintended operations by constructing a gadget chain reusing existing small code sequences (gadgets) collected across the entire code space. In this paper, we propose to address ROP attacks from a different angle-shrinking available code space at runtime. We present ROPStarvation , a generic and transparent ROP countermeasure that defend against all types of ROP attacks with almost zero run-time overhead. ROPStarvation does not aim to completely stop ROP attacks, instead it attempts to significantly increase the bar by decreasing the possibility of launching a successful ROP exploit in reality. Moreover, shrinking available code space at runtime is lightweight that makes ROPStarvation practical for being deployed with high performance requirement. Results show that ROPStarvation successfully reduces the code space of target applications by 85%. With the reduced code segments, ROPStarvation decreases the probability of building a valid ROP gadget chain by 100% and 83% respectively, with the assumptions that whether the adversary knows the vulnerable applications are protected by ROPStarvation . Evaluations on the SPEC CPU2006 benchmark show that ROPStarvation introduces nearly zero (0.2% on average) run-time performance overhead.

There is a growing interest in the open-source hardware movement to amortize non-recurring engineering costs by using plug-and-play system-on-chip (SoC) designs, where the communication among different components is provided by an on-chip interconnection network. Unfortunately, building an on-chip network (OCN) that is suitable for a specific SoC design requires the exploration of a large number of design options and involves diverse research methodologies to evaluate performance, area, energy, and timing. In this paper, we propose PyOCN, a unified framework that vertically integrates multiple research methodologies to enable productively exploring the OCN design space. PyOCN is the first comprehensive framework for modeling (e.g., functional-level, cycle-level, and register-transfer-level), testing (e.g., unit testing, integration testing, and property-based random testing), and evaluating (e.g., simulating, generating, and characterizing) on-chip interconnection networks. We use a case study based on a 64-terminal butterfly network to illustrate the key features of PyOCN and to demonstrate the framework's potential in productively modeling, testing, and evaluating OCNs.

This paper proposes and experimentally assesses an online capacitor condition monitoring algorithm for use with a drive system using an open-end winding topology. The proposed algorithm periodically evaluates the dc-link capacitance during a capacitor discharging state when the motor is at standstill. Expressions of capacitor voltage and current are derived for discharging cycle and provide key information for capacitance estimation using a recursive least square method. Also, the operation range of the proposed algorithm is extended to multiple insulated gate bipolar transistor failure conditions in the inverter. Experimental results verify that the proposed algorithm is capable of identifying capacitor deterioration from both healthy and postfault state for a 3010 uF capacitor (450V 9.8A). but the estimation accuracy is reduced for 438 uF capacitor (385V 2.7A).

In this paper, we study a wireless networked control system (WNCS) with $N \ge 2$ sub-systems sharing a common wireless channel. Each sub-system consists of a plant and a controller and the control message must be delivered from the controller to the plant through the shared wireless channel. The wireless channel is unreliable due to interference and fading. As a result, a packet can be successfully delivered in a slot with a certain probability. A network scheduling policy determines how to transmit those control messages generated by such $N$ sub-systems and directly influences the transmission delay of control messages. We first consider the case that all sub-systems have the same sampling period. We characterize the stability condition of such a WNCS under the joint design of the control policy and the network scheduling policy by means of $2^N$ linear inequalities. We further simplify the stability condition into only one linear inequality for two special cases: the perfect-channel case where the wireless channel can successfully deliver a control message with certainty in each slot, and the symmetric-structure case where all sub-systems have identical system parameters. We then consider the case that different sub-systems can have different sampling periods, where we characterize a sufficient condition for stability.

The receiver array used by the modern synthetic aperture sonar (SAS) may confront the issue that some receivers fail to work. Generally, the failed receivers would affect the imaging performance if the echoed signal of failed receivers were not recovered. In order to solve this problem, this paper first recovers the data of the failed receivers based on the method of the linear prediction. Then, the range Doppler algorithm based on the phase centre approximation is exploited to focus the multireceiver data. At last, the simulated data is used to validate the presented method.

Based on the phase centre approximation (PCA), the imagery of the multireceiver synthetic aperture sonar (SAS) can be converted to the data processing of the monostatic SAS. When it comes to the monostatic conversion, there are two methods, i.e. the conversion in the 2-D space domain and that in the Doppler domain. This paper summarizes two preprocessing methods. Then, the simulations with the uniform and nonuniform sampling cases are used to demonstrate both preprocessing methods. The imaging results show that the preprocessing in the Doppler domain can be widely used as the imaging performance is superior to that with the preprocessing in the 2-D space domain.

This paper proposes a new lossless bi-directional current sense circuit for low-voltage high-current bi-directional converters. Lossless current sensing is achieved by compensating the inductance of the inductor with a low pass filter. A new structure which adopts floating power rail, dc-biased current mirror and closed loop operation level-shifts and amplifies the output of the low pass filter. The difference between the output voltage and the reference voltage is proportional to the inductor current. The proposed circuit realizes high bandwidth bi-directional estimation of instantaneous inductor current without using costly high performance operational amplifiers. The elimination of the external current-sense resistor greatly improves the efficiency of the converter and the proposed circuit can be integrated into a variety of efficiency-critical high-current converters. The novel circuit is constructed and tested with a bi-directional converter. Experimental results demonstrate good agreement with theory and verify the excellent linearity and high bandwidth capacities of the circuit.

The focusing performance and the focusing efficiency are the two important issues for the multireceiver synthetic aperture sonar (SAS) system. Nowadays, the former one is not important any more as the performance of most imaging algorithms is more or less the same with each other. In other words, the latter one mostly limits the engineering application of the SAS system. In order to satisfy the real time processing of the multireceiver SAS data, the focusing method is usually developed by the parallel algorithm. In this paper, the Intel® math kernel library is used to develop the imaging algorithm, which can improve the focusing efficiency without loss of imaging performance. At last, the real data is used to demonstrate the presented method.

Wearable devices are now leveraging multi-core processors to cater to the increasing computational demands of the applications via multi-threading. However, the power, performance constraints of many wearable applications can only be satisfied when the thread-level parallelism is coupled with hardware acceleration of common computational kernels. The ASIC accelerators with high performance/watt suffer from high non-recurring engineering costs. Configurable accelerators that can be reused across applications present a promising alternative. Autonomous configurable accelerators loosely-coupled to the processor occupy additional silicon area for local data and control and incur data communication overhead. In contrast, configurable instruction set extension (ISE) accelerators tightly integrated into the processor pipeline eliminate such overheads by sharing the existing processor resources. Yet, naively adding full-blown ISE accelerators to each core in a many-core architecture will lead to huge area and power overheads, which is clearly infeasible in resource-constrained wearables. In this paper, we propose Stitch, a many-core architecture where tiny, heterogeneous, configurable and fusible ISE accelerators, called polymorphic patches are effectively enmeshed with the cores. The novelty of our architecture lies in the ability to stitch together multiple polymorphic patches, where each can handle very simple ISEs, across the chip to create large, virtual accelerators that can execute complex ISEs. The virtual connections are realized efficiently with a very lightweight compiler-scheduled network-on-chip (NoC) with no buffers or control logic. Our evaluations across representative wearable applications show an average 2.3X improvement in runtime for Stitch compared to a baseline many-core processor without ISEs, at a modest area and power overhead.

In this paper, the distributed optimal consensus algorithms for general linear multi-agent systems are considered. The dynamics for the N agents are independent and homogeneous. The quadratic cost consists of three terms, one corresponds to the importance of approaching the destination (consensus value), the second term corresponds to the importance of formation maintenance, and the third term is the total expended energy. Under the following three conditions, the graph is connected, the subsystem is controllable, and the weighted matrices of the cost function satisfy that one Riccati equation and one Lyapunov equation have the same positive definite solution, we can get the distributed optimal controller and the system can be consensusable. The solutions of this paper consist of some existing results as the special cases.

This paper studies the problem of designing distributed state estimators for a class of large-scale interconnected systems. The goal is to design a local state estimator for each subsystem using local information and state estimates exchanged from neighboring subsystems. A Kalman-like distributed estimation strategy is considered where the interacting terms from neighboring subsystems are replaced with their estimates. We first show that this Kalman-like distributed estimator is not always stable, a property always enjoyed by the standard Kalman filter. Then several sufficient conditions are provided for testing the stability of the distributed estimator.

New media arts are an innovative genre of artworks in which artistic expression is explored and developed by the artist. This genre of new media arts is created in a vast number of ways. Currently, digitized collection systems are commonly used by galleries and museums for traditional art [1]. The need for documentation and archiving complex new media artworks is now increasingly crucial for future preservation and representation. This study aims to establish criteria of aesthetic media representation for media archived in an interactive digital space and explores a generic solution for an interactive digital space. Based on the Interactive Art Taxonomy [2], visitors to the digital space can create, interact, and experience the new media art. This taxonomy demonstrates that archiving of the content can take place for documentation and future preservation in the strategic context for the creation. This digital archiving process proposed will be a useful model to be adopted or adapted by universities, museums, and other institutions in terms of archiving media arts practices.

In Malaysia, the main focus of Jabatan Kemajuan Orang Asli (JAKOA) is helping aboriginal people on various aspects in their lives. For example, education, accommodation, basic survival skills and other facilities for this group of people to adapt and survive in modern times of Malaysia [1]. However, are these efforts enough? The Mah-Meri people are one of the nineteen tribes of aboriginal people in Malaysia. The homeland of this ethnic tribe is situated in Carey Island, located less than forty miles from Kuala Lumpur, hidden in plain sight. The Mah-Meri tribes survives by producing creative handy crafts such as wood carvings and weavings to keep themselves afloat in these challenging times. The ancestral skills and stories of their ethnic tribe are passed down by word and mouth from generation to generation. However as the society moves towards the future, many of the skills and stories are forgotten and lost [2]. Some of the Mah-Meri people have moved on working in the city and there are still a portion of them continuing the legacy. Due to that, it has arisen that the Tompoq Tompoh Mah-Meri Women's ‘First Weave’ project, states that it is obvious and that there is a need to document their oral tradition and culture [2]. In this paper, the documentation of the Mah-Meri wood carving shall be presented in a digital platform. The demand of interactive systems are flooding the technology industry where every individual are now armed or equipped with a digital device [3]. Interactive systems play an important role in the effort of preserving the Mah-Meri tribe's culture and heritage. In this paper, a documentation journey of the Mah-Meri wood carving process into digital platform will be discussed. The final output of the prototype targeted to users of the Malaysian public and international audience.

Cryptographic algorithm plays a significant role in a cryptosystem, which protects those sensitive and private data from been obtained by some malicious attackers. Actually, the details about the cryptographic algorithm applied in a cryptosystem are often unknown to one cryptanalyst. When a cryptanalyst works on cryptanalysis, he will have much trouble if he doesn't know anything about the used cryptographic algorithm. In this paper, we introduce an approach to identifying the cryptographic algorithm with no other information but ciphertext. Firstly, we present the whole implementation architecture of our identification system. Then we apply our identification system in identifying 5 common block ciphers, namely AES, Blowfish, 3DES, RC5 and DES. Through analyzing the experiment results, we conclude that the identification rate can obtain around 90% if keys are the same for training and testing ciphertexts. When we use different keys for training and testing ciphertexts, we can still identify AES from anyone of the other 4 cryptographic algorithms with a high identification rate in one to one identification.

With the extensive use of differential protection in micro-grid, the demand for online obtaining the settings becomes more urgent than the process in the past. This paper proposes a new differential protection scheme for micro-grid where a settings tracking and providing scheme is implemented to acquire the latest enabled protection settings by tracking multiple setting group control block (SGCB) class services. A machine learning technique is implemented to assist classifier in identifying the most relevant electrical features which are required for the fault detection and to establish the best efficient differential protection strategy to micro-grid. A practical case study has successfully verified the adaptability and practicability of the micro-grids protection scheme where statistical classifier will make a decision based on protection settings and differential features.

Switched inverters generate fast rates of change of common-mode voltage and are an unwanted side-effect in variable speed drive systems operated with PWM inverters. Whilst techniques have been reported that theoretically eliminate the common-more voltage, when the dead-time effects and the practical transient performance of semiconductors are considered, a common-mode voltage is still generated, even though these proposed techniques sacrifice dc-link utilization and switching loss. In this paper, a switching strategy is proposed for the three-level five-phase neutral-point-clamped inverter, which reduces the common-mode voltage as far practically possible and eliminates vectors in the d 2 q 2 plane. The proposed method maintains the same linear modulation range as the conventional space vector modulation technique but utilises fewer switching actions in one carrier period. Moreover, its complexity is reduced lowering the computational overhead. The proposed method is verified in both simulation and experiments on a prototype of five-phase neutral-point-clamped inverter.

In recent years, with more and more people shopping, chatting and video online, the Internet is playing a more and more important role in human's daily life. Since the Internet is so close to our lives, it contains so much personal information that will cause a lot of troubles or even losses when divulged. So it's necessary and urgent to find a efficient way to detect the abnormal network behavior. In this paper, we present a new detection method based on compound session. In contrast to previous methods, our approach is based on the cloud computing platform and the cluster system, using Hadoop Distributed File System (HDFS) to analysis and using Twitter Storm to make real-time network anomaly detection come true.