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Unprecedented levels of device connectivity and the emergence of futuristic digital services are driving fundamental changes to underlying fixed and wireless data transport networks. Projected bandwidth requirements, coupled with increased network centralization and virtualization, will lead to the convergence of data-center, fixed and wireless systems, and a greater onus being placed on the optical routing/transport portion of these networks. Such converged networks will require the development of optical technologies capable of servicing a multitude of network user types. In this work, we propose the use of a Silicon Photonic (SiP) space-and-wavelength selective switch fabric as a flexible wavelength provisioning platform for converged optical networks. The envisaged converged network is presented and an experimental test-bed which demonstrates flexible Cloud Radio Access Networking (C-RAN), using a 4 × 4 micro-ring resonator based switch, is described. Successful provisioning and transmission of Wavelength Division Multiplexed (WDM) based analog Radio-over-Fiber (RoF) services, over 10 km of fiber, in the converged test-bed is demonstrated and evaluated in terms of the received Bit Error Rate (BER) and Error Vector Magnitude (EVM). Furthermore, the wavelength multi-casting capabilities of the SiP switch is shown to enable dynamic resource allocation in the optical domain, and this is highlighted through the experimental implementation and evaluation of two C-RAN use cases - representing high and low mobile traffic demand scenarios. [ABSTRACT FROM AUTHOR]

Deep learning is revolutionizing many aspects of our society, addressing a wide variety of decision-making tasks, from image classification to autonomous vehicle control. Matrix multiplication is an essential and computationally intensive step of deep-learning calculations. The computational complexity of deep neural networks requires dedicated hardware accelerators for additional processing throughput and improved energy efficiency in order to enable scaling to larger networks in the upcoming applications. Silicon photonics is a promising platform for hardware acceleration due to recent advances in CMOS-compatible manufacturing capabilities, which enable efficient exploitation of the inherent parallelism of optics. This article provides a detailed description of recent implementations in the relatively new and promising platform of silicon photonics for deep learning. Opportunities for multiwavelength microring silicon photonic architectures codesigned with field-programmable gate array (FPGA) for pre- and postprocessing are presented. The detailed analysis of a silicon photonic integrated circuit shows that a codesigned implementation based on the decomposition of large matrix-vector multiplication into smaller instances and the use of nonnegative weights could significantly simplify the photonic implementation of the matrix multiplier and allow increased scalability. We conclude this article by presenting an overview and a detailed analysis of design parameters. Insights for ways forward are explored. [ABSTRACT FROM AUTHOR]

Widespread adoption of silicon photonics into datacenters requires that the integration of the driving electronics with the photonics be an essential component of transceiver development. In this article, we describe our silicon photonic transceiver design: a 2.5D integrated multi-chip module (MCM) for 4-channel wavelength division multiplexed (WDM) microdisk modulation targeting 10 Gbps per channel. A silicon interposer is used to provide connectivity between the photonic integrated circuit (PIC) and the commercial transimpedance amplifiers (TIAs). Error free modulation is demonstrated at 10 Gbps with −16 dBm received power for the photonic bare die and at 6 Gbps with −15 dBm received power for the first iteration of the MCM transceiver. In this context, we outline the different integration approaches currently being employed to interface between electronics and photonics—monolithic, 2D, 3D, and 2.5D—and discuss their tradeoffs. Notable demonstrations of the various integration architectures are highlighted. Finally, we address the scalability of the architecture and highlight a subsequent prototype employing custom electronic integrated circuits (EICs). [ABSTRACT FROM AUTHOR]

Deep learning has been revolutionizing many aspects of our society, powering various fields including computer vision, natural language processing, and activity recognition. However, the scaling trends for both datasets and model size are constraining system performance. Variability of memory requirements can lead to poor resource utilization. Reconfigurable photonic interconnects provide scalable solutions and enable efficient use of disaggregated memory resources. We propose a photonic switched optically connected memory system architecture that tackles the memory challenges while showing the functionality of optical switching for deep learning models. Our proposed system architecture utilizes a “lite” (de)serialization scheme for memory transfers via optical links to avoid network overheads and supports the dynamic allocation of remote memories to local processing systems. In order to test the feasibility of our proposal, we built an experimental testbed with a processing system and two remote memory nodes using silicon photonic switch fabrics and evaluated the system performance. The optical switching time is measured to be 119 μs and an overall 2.78 ms latency is achieved for the end-to-end reconfiguration. The collective results and existing high-bandwidth optical I/Os show the potential of integrating the photonic switched optically connected memory to state-of-the-art processing systems. [ABSTRACT FROM AUTHOR]

We demonstrate the first multi-stage 8 × 8 silicon photonic switch with switching elements based on dual add-drop microrings with a compact footprint of 4 mm2. This device leverages co-design of the switch architecture and the switching elements with a well-balanced set of performance metrics. The switching elements are designed to have a 3-dB optical passband of 165 GHz, exhibiting off- and on-resonance losses of 0.67 dB and 2 dB, respectively. Full characterization of all switch paths shows an end-to-end on-chip loss between 4.4 and 9.6 dB, with worst-case crosstalk leakage averaged at −16 dB. Owing to the efficient doped waveguide thermo-optic phase shifters, the device features a tuning efficiency of 48.85 GHz/mW. The reconfiguration time of the switch fabric is measured to be 1.2 μs and 0.5 μs at the rise and fall edge, respectively. The dual-microring switching element together with the multi-stage architecture preserves an end-to-end passband over 55 GHz. We validate the switch performance with optical paths of varying numbers of on- and off-resonance switching elements – less than 2 dB power penalties are obtained for all data routings at 32 Gbps. [ABSTRACT FROM AUTHOR]

We propose and analyze a scalable microring-based Clos switch fabric architecture constructed with switch-and-select switching stages. A silicon 4 × 4 building block that was designed and fabricated through American Institute for Manufacturing Integrated Photonics is used for the proof-of-principle demonstration of a 16 × 16 Clos switch fabric. By fully blocking the first-order crosstalk, the 4 × 4 device is measured to show a crosstalk ratio in the range of –57 to –48.5 dB, enabling better than –39 dB crosstalk for the 16 × 16 switch. Our study shows that the three-stage Clos design enables up to a factor of 4 in the reduction of the number of switching cells compared to single-stage switch-and-select fabrics. We further explore the design space for both first-order and second-order switching elements using the foundry-validated parameters and how these factors impact the performance and scalability of the three-stage Clos switch. A detailed power penalty map is drawn for Clos switch fabrics with various scales, which reveals that the ultimate key limiting factor is the shuffle insertion loss. An optimized 32-port Clos switch fabric using foundry-enabled parameters is shown to have a less than 10-dB power penalty. [ABSTRACT FROM AUTHOR]

In this paper, we propose a joint frequency-domain equalizer (FDE) and maximum likelihood sequence detection (MLSD) algorithm to eliminate the serious inter-symbol interference for 56-Gbit/s optical faster-than-Nyquist 4-level pulse-amplitude modulation (FTN-PAM4) system using 10 G-class optics. The simplified FDE structure is first designed to replace the feed-forward equalization (FFE) and post filter structure in conventional joint FFE, post filter and MLSD algorithm. In the joint algorithms, the simplified FDE structure has approximately $13\%$ and $1\%$ computational complexity compared to FFE with least-mean-square (FFE-LMS) adaptive algorithm and FFE with recursive-least-squares (FFE-RLS) adaptive algorithm, respectively. Therefore, the proposed joint FDE and MLSD algorithm has much lower computational complexity than the conventional joint FFE, post filter and MLSD algorithm. Meanwhile, the experimental results show that the performance of joint FDE and MLSD algorithm is better than that of joint FFE-LMS, post filter and MLSD algorithm, and is similar with that of joint FFE-RLS, post filter and MLSD algorithm. In conclusion, the proposed joint FDE and MLSD algorithm has both low computational complexity and excellent performance for optical FTN-PAM4 systems, which shows its potential for applications in low-cost and low-power short-reach optical interconnects. [ABSTRACT FROM AUTHOR]

We propose a universal and analytic step-by-step method to calculate the optimal 90° and 180° waveguide bends (L-bends and U-bends) in silicon-on-insulator photonics platform. This approach consists of first building an analytic model of loss per unit length as a function of radius of curvature and then using a variational optimization of the bending loss. It is shown that the shape of the optimal bends is ultimately determined either by the radiation loss of tight bends if the curvature of the bend is set to eliminate mode-mismatch losses or by the sidewall roughness loss if the radius of curvature is large. Numerical results from full wave simulations and comparison of the optimal bend with the Bezier, Euler, and Hybrid Euler-Circular bend are also provided to show the validity of our approach. [ABSTRACT FROM AUTHOR]

A detailed analysis of fundamental tradeoffs between ring radius and coupling gap size is presented to draw realistic borders of the possible design space for microring resonators (MRRs). The coupling coefficient for the ring-waveguide structure is estimated based on an integration of the nonuniform gap between the ring and the waveguide. Combined with the supermode analysis of two coupled waveguides, this approach is further expanded into a closed-form equation that describes the coupling strength. This equation permits to evaluate how the distance separating a waveguide from a ring resonator, and the ring radius, affect coupling. The effect of ring radius on the bending loss of the ring is furthermore modeled based on the measurements for silicon MRRs with different radii. These compact models for coupling and loss are subsequently used to derive the main optical properties of MRRs, such as 3-dB optical bandwidth, extinction ratio of resonance, and insertion loss, hence identifying the design space. Our results indicate that the design space for add-drop filters in a wavelength division multiplexed link is currently limited to 5–10 $\mu$ m in radius and gap sizes ranging from 120 to 210 nm. The good agreement between the results from the proposed compact model for coupling and the numerical FDTD and experimental measurements indicate the application of our approach in realizing fast and efficient design space exploration of MRRs in silicon photonic interconnects. [ABSTRACT FROM AUTHOR]

In this letter, we propose layered/enhanced asymmetrically clipped optical single-carrier frequency-division multiplexing (L/E-ACO-SCFDM) for optical-wireless communications. L/E-ACO-SCFDM has a lower computational complexity and peak-to-average power ratio (PAPR) than L/E-ACO orthogonal frequency-division multiplexing (L/E-ACO-OFDM). The computational complexity of the simplified transmitter in L/E-ACO-SCFDM with $R$ layers is $(2-2/2^{R})O(N)$ , which is lower than the computational complexity of $(2-2/2^{R})O(N\text {log}_{2}N)$ in L/E-ACO-OFDM. At a complementary cumulative distribution function of $10^{-3}$ , the PAPR of L/E-ACO-SCFDM is approximately 4.2, 3.4, and 2.7 dB lower than that of L/E-ACO-OFDM for 2, 3, and 4 layers, respectively. The simulation results indicate that L/E-ACO-SCFDM has better performance than L/E-ACO-OFDM under the transmitter nonlinearity and multipath fading. [ABSTRACT FROM AUTHOR]

In this letter, we experimentally demonstrated a 40-Gbit/s 256-quadrature amplitude modulation (256-QAM) interleaved single-carrier frequency-division multiplexing (I-SC-FDM) over 10-km standard single-mode fiber (SSMF) for optical interconnects. I-SC-FDM has lower peak-to-average power ratio and lower computational complexity of transmitter compared with orthogonal frequency division multiplex- ing (OFDM). High-level QAM can achieve high spectral efficiency; however, it is susceptible to both linear and nonlinear distortions. The frequency-domain one-tap equalizer and the time-domain decision-feedback equalizer with recursive least square and Volterra algorithm are jointly employed to eliminate the distortions for the 256-QAM I-SC-FDM. After 10-km SSMF, I-SC-FDM has better performance than localized SC-FDM and OFDM. Therefore, I-SC-FDM shows the potential for short-reach optical interconnects. [ABSTRACT FROM PUBLISHER]

Power density and cooling issues are limiting the performance of high performance chip multiprocessors (CMPs), and off-chip communications currently consume more than 20% of power for memory, coherence, PCI, and Ethernet links. Photonic transceivers integrated with CMPs are being developed to overcome these issues, potentially allowing low hop count switched connections between chips or data center servers. However, latency in setting up optical connections is critically important in all computing applications, and having transceivers integrated on the processor chip also pushes other network functions and their associated power consumption onto the chip. In this paper, we propose a low latency optical switch architecture that minimizes the power consumed on the processor chip for two scenarios: multiple-socket shared memory coherence networks and optical top-of-rack switches for data centers. The switch architecture reduces power consumed on the CMP using a control plane with a simplified send and forget server interface and the use of a hybrid Mach-Zehnder interferometer and semiconductor optical amplifier integrated optical switch with electronic buffering. Results show that the proposed architecture offers a 42% reduction in head latency at low loads compared with a conventional scheduled optical switch as well as offering increased performance for streaming and incast traffic patterns. Power dissipated on the server chip is shown to be reduced by more than 60% compared with a scheduled optical switch architecture with ring resonator switching. [ABSTRACT FROM PUBLISHER]

We review possible architectures for 400 Gigabit Ethernet links based on advanced modulation formats for the first time. Their optical link power budget, digital complexity, and power dissipation are compared via simulations. The challenges of implementing the physical layer are discussed. [ABSTRACT FROM PUBLISHER]