32 results on '"Cheng, Junji"'
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2. Optimization of Specific ON-Resistance of Superjunction Device with Two-Zones Variation Vertical Doping Profile
3. A Rigorous Analysis of Specific ON-resistance for 4H-SiC Superjunction Devices
4. Superjunction SiC TCOX-MOSFET: Study and Comparison
5. A Novel Insulating-Pillar Superjunction with Vertical Insulators: Breakthrough of Specific ON-Resistance Limit
6. A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron,sp
7. A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances
8. Optimization and Comparison of Specific ON-Resistance for Superjunction MOSFETs Considering Three-Dimensional and Insulator-Pillar Concepts.
9. Simulation Study of a p -GaN HEMT With an Integrated Schottky Barrier Diode.
10. Study on Conductivity Degradation of High-k VDMOS Caused by Ferroelectricity
11. A New Carrier Stored Trench IGBT Realizing Both Ultra Low $V_{\text{on}}$ and Turn-off loss
12. Study on A Novel Trench LDMOS with Double Deep Trenches and Superjunction
13. A Lateral Power p-Channel Trench MOSFET Improved by Variation Vertical Doping.
14. Optimization and Comparison of Drift Region Specific ON-Resistance for Vertical Power Hk MOSFETs and SJ MOSFETs With Identical Aspect Ratio.
15. Simulation Study of a Novel Snapback Free Reverse-Conducting SOI-LIGBT With Embedded P-Type Schottky Barrier Diode.
16. A Novel IGBT With High-k Dielectric Modulation Achieving Ultralow Turn-Off Loss.
17. A TCAD Study on Lateral Power MOSFET With Dual Conduction Paths and High- $k$ Passivation.
18. A Novel Diode-Clamped Carrier Stored Trench IGBT With Improved Performances.
19. A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS
20. The Oppositely Doped Islands IGBT Achieving Ultralow Turn Off Loss.
21. A 600-V Super-Junction pLDMOS Utilizing Electron Current to Enhance Current Capability.
22. Simulation Study of a p-LDMOS With Double Electron Paths to Enhance Current Capability.
23. A High-Voltage ?Quasi-p-LDMOS? Using Electrons as Carriers in Drift Region Applied for SPIC.
24. A TIGBT With Floating n-Well Region for High dV/dt Controllability and Low EMI Noise.
25. An Improved SOI P-Channel LDMOS With High- k Gate Dielectric and Dual Hole-Conductive Paths.
26. Multilevel Low-Voltage Power Supplies Capable of Integrating With High-Voltage Devices.
27. A versatile low-cost smart power technology platform for applications over broad current and voltage ranges
28. Low specific on-resistance p-type OPTVLDLDMOS with double hole-conductive paths for SPIC application
29. A novel low-side structure for OPTVLD-SPIC technologically compatible with BiCMOS.
30. New Planar Junction Edge Termination Technique Using OPTVLD With a Buried Layer.
31. A Low On-State Voltage and Saturation Current TIGBT With Self-Biased pMOS.
32. A Practical Approach to Enhance Yield of OPTVLD Products.
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