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We report on an study of the GaP/Si interface for application in silicon heterojunction solar cells. We analyzed the band alignment using X-ray photoelectron spectroscopy (XPS) and cross-sectional Kelvin probe force microscopy (x-KPFM). Our measurements show a high conduction band offset (0.9 eV) leading to a barrier in electron extraction which we microscopically resolved via x-KPFM. XPS reveals the presence of Si-Ga bonds which explains the observed interface dipole that leads to low open circuit voltage and low fill factor in GaP/Si heterojunction solar cells. Furthermore, we investigated the electronic and morphologic changes in GaP upon Si and Mg doping.

The world record efficiency and open circuit voltage for crystalline silicon solar cells are held by a-Si/Si heterojunction devices. While a-Si provides excellent surface passivation, these heterojunction devices are limited by non-ideal optical and electronic properties. Gallium phosphide is a candidate material for replacing a-Si in a heterojunction device, promising lower parasitic absorption and better carrier mobilities. In this work, we present our results in growing high quality GaP thin films directly on Si using a two-step nucleation and growth scheme with metalorganic chemical vapor deposition, characterization, and x-ray photoelectron spectroscopy band offset measurements toward realizing a GaP/Si heterojunction device.

Tandem Ga_(1-x)In_xP/Si microwire array solar cells are a route towards a high efficiency, low cost, flexible, wafer-free solar technology. Coupled full-field optical and device physics simulations of a Ga_(0.51)In_(0.49)P/Si wire array tandem are used to predict device performance. A 500 nm thick, highly doped “buffer” layer between the bottom cell and tunnel junction is assumed to harbor a high density of lattice mismatch and heteroepitaxial defects. Under simulated AM1.5G illumination, the device structure explored in this work has a simulated efficiency of 23.84% with realistic top cell SRH lifetimes and surface recombination velocities. The relative insensitivity to surface recombination is likely due to optical generation further away from the free surfaces and interfaces of the device structure. To move towards realizing these device structures, GaP and Ga_(1-x)In_xP layers were grown heteroepitaxially with metalorganic chemical vapor deposition on Si microwire array substrates. The layer morphology and crystalline quality have been studied with scanning electron microscopy and transmission electron microscopy, and they provide a baseline for the growth and characterization of a full device stack.

Silicon microwire arrays have recently demonstrated their potential for low cost, high efficiency photovoltaics. These high aspect ratio, radial junction wire arrays allow for the absorption of nearly all the incident sunlight while enabling efficient carrier extraction in the radial direction. One of the remaining challenges to make this technology commercially viable is scaling up of the microwire array growth. We discuss here a technique we have developed for vapor liquid solid growth of microwire arrays over full six-inch wafers using a cold-wall RF-heated chemical vapor deposition furnace. This geometry allows for fairly uniform growth over large areas, rapid cycle time, and improved run-to-run reproducibility. We have studied these large-area microwire arrays using scanning electron microscopy and confocal microscopy to assess their structural fidelity and uniformity. We have also developed a technique to embed these large-area arrays in polymer and peel them off the substrate, which could enable lightweight, flexible solar cells with efficiencies as high as crystalline Si solar cells. We have tested the energy conversion properties of these microwire array samples grown using a liquid junction contact and a photoelectrochemical cell. Initial efficiencies measured in this way suggest that the material quality of these microwire arrays is similar to earlier small-area wire arrays that we have grown, meaning that this technique is a viable way to scale up microwire array devices.