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The effect of flatband-voltage reduction [roll-off (R-O)], which limits fabrication options for obtaining the needed band-edge threshold voltage values in transistors with highly scaled metal/high-k dielectric gate stacks, is discussed. The proposed mechanism causing this R-O phenomenon is suggested to be associated with the generation of positively charged oxygen vacancies in the interfacial SiO2 layer next to the Si substrate. The vacancies in the interfacial layer are induced by oxygen outdiffusing into the overlying high-k dielectric. The model is consistent with the variety of observations of R-O dependence on the electrode and substrate type, high-k dielectric composition and thickness, temperature, etc. The model's predictions were experimentally verified. [ABSTRACT FROM AUTHOR]

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks. [ABSTRACT FROM PUBLISHER]

High work function (4.9 eV) on high-κ gate dielectric, which is suitable for bulk p-MOSFET, has been achieved using fully silicided (FUSI) Pt∞Si gate without boron predoping of polysilicon. High concentration of Pt in FUSI Pt∞Si using Ti capping layer on Pt in the FUSI process is a key to achieving high work function and reduced Fermi-level pinning on high-κ dielectric. By combining with substituted Al (SA) gate for nMOSFET, a wide range of work function difference (0.65 eV) between n and pMOSFETs is demonstrated, without any adverse effects of polysilicon predoping. [ABSTRACT FROM AUTHOR]

Substituted aluminum (SA) metal gate on high-κ gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved for a Ti-Al-polysilicon-HfAION gate structure by a low-temperature annealing at 450 °C. The SA gate on HfAION dielectric shows a very low work function of 4.25 eV, which is well suitable for bulk nMOSFETs. The SA process is fully free from the Fermi-level pinning problem. In addition, the SA process also shows improved uniformity in leakage current distribution compared to fully silicided metal gate. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, thermally stable fully silicided (FUSI) Hf-silicide gate electrode whose workfunction (4.2 eV) is very close to that of n+ polysilicon. No polyslicon depletion effect and excellent thermal stability with negligible change in equivalent oxide thickness and flatband voltage even after high-temperature annealing at 950 °C are demonstrated. These results indicate that FUSI Hf-silicide is a promising candidate for n-MOSFET metal-gate electrode for dual-metal CMOS process. [ABSTRACT FROM AUTHOR]

We propose and demonstrate a novel approach for dual metal gate CMOS process integration through the use of a very thin aluminum nitride (AIN[sub x]) buffer layer between metal and gate oxide. This buffer layer prevents the gate oxide from being exposed to a metal etching process which potentially causes oxide thinning and damage. Subsequent annealing consumes the very thin AIN[sub x] layer and converts it into a new metal alloy film by reacting with gate metals, resulting in no increase in EOT due to this buffer layer. The work function of the original gate metal is also modified as a result of its reaction with AIN[sub x], making this approach extremely attractive for engineering the work function for dual metal gate CMOS applications. [ABSTRACT FROM AUTHOR]

We demonstrate a top-surface aluminized and nitrided HfO2 gate dielectric using a synthesis of ultrathin aluminum nitride (AIN) and HfO2. The reaction of AlN with HfO2 through a subsequent high-temperature annealing incorporates Al and N into an HfO2 layer, which results in a synthesis of HfAlON near the top surface of HfO2, forming an HfAlON-HfO2 stack structure. This approach suppresses interfacial layer growth and improves thermal stability of the dielectric, resulting in significant improvement in leakage current. It also shows no adverse effects caused by N and Al incorporation at the bottom interface. [ABSTRACT FROM AUTHOR]