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Your search keyword '"Chang, Y.‐J."' showing total 26 results
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26 results on '"Chang, Y.‐J."'

1. Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

Author

Sell, B., primary, An, S., additional, Armstrong, J., additional, Bahr, D., additional, Bains, B., additional, Bambery, R., additional, Bang, K., additional, Basu, D., additional, Bendapudi, S., additional, Bergstrom, D., additional, Bhandavat, R., additional, Bhowmick, S., additional, Buehler, M., additional, Caselli, D., additional, Cekli, S., additional, Chaganti, Vrsk., additional, Chang, Y. J., additional, Chikkadi, K., additional, Chu, T., additional, Crimmins, T., additional, Darby, G., additional, Ege, C., additional, Elfick, P., additional, Elko-Hansen, T., additional, Fang, S., additional, Gaddam, C., additional, Ghoneim, M., additional, Gomez, H., additional, Govindaraju, S., additional, Guo, Z., additional, Hafez, W., additional, Haran, M., additional, Hattendorf, M., additional, Hu, S., additional, Jain, A., additional, Jaloviar, S., additional, Jang, M., additional, Kameswaran, J., additional, Kapinus, V., additional, Kennedy, A., additional, Klopcic, S., additional, Krishnan, D., additional, Leib, J., additional, Lin, Y.-T., additional, Lindert, N., additional, Liu, G., additional, Loh, O., additional, Luo, Y., additional, Mani, S., additional, Mleczko, M., additional, Mocherla, S., additional, Packan, P., additional, Paik, M., additional, Paliwal, A., additional, Pandey, R., additional, Patankar, K., additional, Pipes, L., additional, Plekhanov, P., additional, Prasad, C., additional, Prince, M., additional, Ramalingam, G., additional, Ramaswamy, R., additional, Riley, J., additional, Perez, J. R. Sanchez, additional, Sandford, J., additional, Sathe, A., additional, Shah, F., additional, Shim, H., additional, Subramanian, S., additional, Tandon, S., additional, Tanniru, M., additional, Thakurta, D., additional, Troeger, T., additional, Wang, X., additional, Ward, C., additional, Welsh, A., additional, Wickramaratne, S., additional, Wnuk, J., additional, Xu, S. Q., additional, Yashar, P., additional, Yaung, J., additional, Yoon, K., additional, and Young, N., additional

Published
2022
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2. Development of Highly Manufacturable, Reliable, and Energy-Efficient Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM)

Author

Rahaman, S. Z., primary, Chang, Y.-J., additional, Hsin, Y.-C., additional, Yang, S.-Y., additional, Chen, F.-M., additional, Chen, K.-M., additional, Wang, I-J., additional, Lee, H.-H., additional, Chen, G.-L., additional, Su, Y.-H., additional, Shih, C.-Y., additional, Chiu, S.-C., additional, Wei, J.-H., additional, Yen, S.-C., additional, Huang, K.-C., additional, Chen, C.-C., additional, Chen, M.-C., additional, Sheu, S.-S., additional, Lo, W.-C., additional, Chang, S.-Z., additional, See, Y.-C., additional, Deng, D.-L., additional, and Wu, C.-I, additional

Published
2022
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5. A Large Dynamic Range Current Sensor Using Magnetic Tunnel Junction on 8” Si process line

Author

Wang, D. Y., primary, Wang, I. J., additional, Lin, C. S., additional, Su, J. W., additional, Lee, H. H., additional, Hsin, Y. C., additional, Yang, S. Y., additional, Chang, Y. J., additional, Kuo, Y. C., additional, Su, Y.H., additional, Rahaman, S. Z., additional, Chen, G. L., additional, Li, S. H., additional, Wei, J. H., additional, Huang, K. C., additional, and Wu, C. I., additional

Published
2019
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12. Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding

Author

Ko, C. T., primary, Hsiao, Z. C., additional, Chang, Y. J., additional, Chen, P. S., additional, Huang, J. H., additional, Fu, H. C., additional, Huang, Y. J., additional, Chiang, C. W., additional, Lee, C. K., additional, Chang, H. H., additional, Tsai, W. L., additional, Chen, Y. H., additional, Lo, W. C., additional, and Chen, K. N., additional

Published
2012
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19. Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies.

Author

Ko, C. T., Hsiao, Z. C., Chang, Y. J., Chen, P. S., Huang, J. H., Fu, H. C., Huang, Y. J., Chiang, C. W., Tsat, W. L., Chen, Y. H., Lo, W. C., and Chen, K. N.

Abstract

Cu TSV combination with Cu/Sn micro-joint to form vertical interconnection is a good alternative for 3D integration. The insertion loss of two chip stack was evaluated by simulation to realize the signal transmission effects in high speed digital signaling via TSV and micro-joint interconnect. To satisfy the throughput and cost requirement for mass production in future, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV fabrication, micro-bumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. This paper presents a complete study of structure design, process condition, electrical and reliability assessment of the wafer-level 3D integration scheme. The 3D integration scheme was assessed to be with excellent electrical performance and reliability, and is potentially to be applied for 3D IC applications. [ABSTRACT FROM PUBLISHER]

Published
2011
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24. A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With n[sup+] Amorphous-Silicon Contacts.

Author

Oh, J. H., Kang, D. H., Park, W. H., Jang, J., Chang, Y. J., Choi, J. B., and Kim, C. W.

Subjects
THIN film transistors, FIELD-effect transistors, POLYCRYSTALLINE semiconductors, POLYCRYSTALS, CRYSTALLIZATION, ANNEALING of metals, BIOLUMINESCENCE
Abstract

Abstract-We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) n+ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-μm offset length exhibited a field-effect mobility of 18.3 cm[sup2] /V∙s and minimum OFF-state current of 2.79 x 10[sup-12] A/μm at V[subds] = 5 V. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 cm[sup2]/V ∙ s. [ABSTRACT FROM AUTHOR]

Published
2009
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