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Learning chemistry can be challenging because it involves a lot of abstract and complex concepts. To improve students' learning performance and motivation, this study designs a gamification teaching activity using board game and QR code scanning. This activity applies the Gamification Teaching Model using Card-game, Slides and Learning Sheets (CSLS Gamification Model) for organic chemistry learning. A quasi-experimental design with 151 participants was conducted to evaluate the effectiveness of the activity. The results suggested that the teaching activity using CSLS model could be more helpful in promoting students' understanding of organic chemical structure and functional groups compared to traditional lecture-based teaching model. Furthermore, students generally evaluated the gamification teaching activity as positive and had positive experiences in terms of flow antecedents and experiences. In conclusion, the gamification teaching activity could be effective to promote students' learning performance and motivation. Future research is encouraged to applied the CSLS gamification model to different learning subjects.

The aim of this paper is to compare the learning effectiveness and learning motivation of digital game-based learning between the competitive and the cooperative mode. Forty-seven junior high school students were invited to participate in the learning experiment. The students were divided into two groups and played Fragrance Channel in two different modes. Pre-and post-tests were used to evaluate students' learning effectiveness under different conditions and an IMMS questionnaire was used to evaluate learning motivation. The results show no significant differences for both groups when evaluating learning effectiveness and motivation. However, both groups presented significant differences between their pre-and post-tests conditions when it comes to the acquired knowledge. We identified significant differences also for the satisfaction level showing that students enjoyed it more to play in the competitive mode.

This study aims to develop a recognition system of bodily expressions of emotions (BEE) that can be applied to digital kinetic games. There were three stages of the study. First, 76 emotion and action terms frequently used by teenagers were selected, they were quantized into four quadrants, and gathered into 16 clusters. The second stage is to construct the database of emotional motions. The researchers collected the data of body motions expressed in accordance to the 16 emotion terms, classified the attributions of body motions using the particular factors of Effort and Space Harmony based on Laban Movement Analysis (LMA). The last stage is to construct the algorithms of BEE based on the attribution database built in the earlier stage. Finally, the researchers would compare the results of the digital recognition system with the database that was built in the second stage to secure the accuracy of the recognition system. Once the body recognition system was built, it would be an important research tool and mechanism to recognize the emotional changes of the player during the kinetic game play, and compare the learning conditions with learning effectiveness to do further investigations.

Thin ITO-based PET conductive membranes are the major sensing structure in resistive touch panels for network phones or other applications. However, device failures or malfunctions such as early touch and disagreement between force-applied and touched locations have been reported. By examining the surface profiles, it was found that these membranes have considerable initial out of plane deformation. This could be a sign of membrane buckling since the clamped design could causing additional in-plane compression which could triggering the structural buckling. It is important to analyze the buckling behavior of ITO/PET membranes due to initial imperfection, residual stress, or assembly issues, for developing engineering solutions for quality assurance. In this work, both finite element analyses and essential experimental characterizations are performed as the first step toward solving this problem. In conjunction with our previous study [1], this work mainly focuses on the buckling behavior by considering the effect of the compliance of double side glues and the associated post-buckling behavior. In parallel, several experimental investigations have been conducted for characterizing material properties of the adhesion tapes and the panel surface profile for supporting the buckling and post buckling analyses. By both simulation and experimental investigations, the major control factor for causing malfunction of touch panel could be identified and the corresponding engineering solutions would be developed for enhancing the device reliabilities.

This paper focuses on micro controller unit (MCU) based platform and field oriented control (FOC) algorithm applying 3rd harmonic injection algorithm. The target application of this paper is power chain systems of electric vehicle (EV) and electric scooter (E-Scooter). The MCU based system on chip (SoC) is proposed, called Bison1, and the proposed platform is called Bison1 platform which is including specification I/O controller for motor control and memory with FOC algorithm. The experiment results show the proposed methodology has good performance for complexity FOC algorithm and, the proposed Bison1 platform provides some protected mechanisms such as over heating and over current for safety The execution time for the motor control of the proposed system is about 44.9 us which is almost the same with digital signal processor (DSP) based system.

Adventure education activities are courses that emphasize on first hand experience learning in situated environment with cooperative groups. In this research, Xbox Kinect and Unity 3D game engine are used to develop the two adventure education games. Digital games can solve some of the problems physical adventure education activities face, such as space limitations and dangers. With the simulations, players can experience the unattainable activities in real life, immerse in the collaborative activities, and explore the value of adventure education. From the post-game reflections, players can perceive their roles in the group, understand the mechanism of leadership, and solve problems. Participants' collaborative gaming process will be recorded by computers and observations conducted by researchers to understand participants' social behaviors. Questionnaires and tests will be used to analyze participants' collaboration patterns. It is hoped that the analysis results offer some in-depth perspectives to the field for the future research.

This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm2, average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager.

This paper proposes a novel method of remapping between any amount of individual systems or chips. Any individual system and chip can share a specific address map with other systems over the proposed adaptive memory map switch (AMMS). Because the AMMS is programmable, it allows the dynamic changing on the remapping of target address by setting AMMS. An implemented example is presented here to specify the proposed AMMS can communicate with different system on chip (SoC) platforms to achieve good performance and integrity.

Power consumption is a critical problem for very large scale integration (VLSI) systems, especially in deep-sub micro systems. Due to the systems are more and more complex, the power issue is a challenge for IC (integrated circuits) design. Hence, this paper develops a hybrid low power technology (HLPT) to deal with the different complexity applications. Additionally, the proposed HLPT is from system-level algorithm to physical level. The experimental results are implemented on the embedded system, PAC (parallel architecture core) Duo+, to show the good performance for achieving 90% power saving.

This paper presents an on-line error detection and correction techniques for through silicon via (TSV) in three-dimensional integrated circuit (3-D IC). The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design has good performance in area and TSV overhead and improves the yield of TSV up to 99.9%.

This paper presents an error-correction scheme to enhance the performance of typical CAN bus. The proposed scheme uses Reed-Solomon (R-S) codec to calculate the parity for the transmission of typical CAN bus. Compared with prior work in terms of Hybrid Automatic Repeat Request (HARQ) scheme for CAN bus transmission, the proposed scheme does not modify the standard CAN protocol but insert an R-S codec unit as an error-correction between Electronic Control Unit (ECU) and CAN bus. In other words, the focus of our proposed scheme is not on modifying the fixed CRC codec of the standard structure, but on increasing the performance based on an additional enhancement module. Experimental results show that the execution time of standard CAN bus can be reduced by the proposed scheme for almost half of transmission time on typical design, while accompanying very minor cost when errors are not correctable or without errors.

This paper proposes an efficient built-in self-detection and self-correction techniques to detect and correct error in discrete cosine transform (DCT)/inverse discrete cosine transform (IDCT) based on the biresidue codes. On the other hand, any single bit error of DCT/IDCT can be efficiently detected or corrected. Experimental results show the proposed BISDC architecture has good performance in throughput with reasonable area overhead and high reliability.