91 results on '"Catania V."'
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2. Power-aware selection policy for networks on chip.
3. An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip.
4. An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures.
5. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip.
6. An encoding scheme to reduce power consumption in Networks-on-Chip.
7. Linguistic Modifiers to Improve the Accuracy-Interpretability Trade-Off in Multi-Objective Genetic Design of Fuzzy Rule Based Classifier Systems.
8. Feedforward artificial neural network to estimate iq of mental retarded people from different psychometric instruments.
9. High Performance Computing for Embedded System Design: A Case Study.
10. Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links.
11. An evolutionary fuzzy c-means approach for clustering of bio-informatics databases.
12. Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms.
13. Exploiting Communication Concurrency for Efficient Deadlock Free Routing in Reconfigurable NoC Platforms.
14. Multi-Objective Evolutionary Fuzzy Clustering for High-Dimensional Problems.
15. Genetic Tuning of Fuzzy Rule Deep Structures for Efficient Knowledge Extraction from Medical Data.
16. A Multiobjective Genetic Fuzzy Approach for Intelligent System-level Exploration in Parameterized VLIW Processor Design.
17. Exploring design space of VLIW architectures.
18. Multiobjective optimization of a parameterized VLIW architecture.
19. Multi-objective mapping for mesh-based NoC architectures.
20. A framework for design space exploration of parameterized VLSI systems.
21. Parameterised system design based on genetic algorithms.
22. A general purpose processor oriented to fuzzy reasoning.
23. A high performance processor for applications based on fuzzy logic
24. Exploitation of redundancy for throughput increase in a high speed LAN.
25. A fuzzy decision maker for source traffic control in high speed networks.
26. Extension of LANs interconnection service in metropolitan area.
27. Fault tolerance increasing in token ring LANs.
28. An efficient hardware architecture to support complex fuzzy reasoning.
29. PMt: a tool to monitor performances in distributed systems.
30. Performance evaluation of a partial dynamic declustering disk array system.
31. On the implementation of an optical token-ring LAN.
32. A soft computing approach to hardware software codesign.
33. A framework for a parallel architecture dedicated to soft computing.
34. Spanning tree algorithm for routing in hierarchical MANs.
35. Design of basic hardware gates for efficient fuzzy computing.
36. Design of a VLSI parallel processor for fuzzy computing.
37. Analog gates for a VLSI fuzzy processor.
38. Internetworking data services.
39. Performance analysis of DQDB behaviour with priority levels.
40. Reliability and fault tolerance aspects in an industrial LAN.
41. Design of a VLSI hardware PET decoder.
42. An assessment of resource exploitation using artificial intelligence based traffic control strategies.
43. VLSI hardware architecture for complex fuzzy systems.
44. A modular-network architecture for performance enhancement in extended local area network.
45. A remote bridging technique to increase performability in distributed systems.
46. A modeling framework to evaluate performability parameters in gracefully degrading systems.
47. Enhancing reliability in an industrial LAN: design and performability evaluation.
48. Using fuzzy logic in ATM source traffic control: Lessons and perspectives.
49. A VLSI fuzzy expert system for real-time traffic control in ATM networks.
50. A VLSI fuzzy inference processor based on a discrete analog approach.
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