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Precise and efficient motion prediction and manipulation of micro- and nanoparticles in a complex fluid suspension system under external electric fields has the potential to revolutionize the manufacture of scalable functional nanodevices. However, the physical motion model of the particle based on physical simulation does not consider the effects in the complex fluid suspension system, e.g., boundary conditions, fluid motion, and particle interactions, and often results in imperfect prediction of particle trajectories under the coupled global field. This study proposes a data-driven approach for small-scale particle trajectory prediction by leveraging both physical simulation model and experimental data. Historical function-on-function regression is used to predict experimental trajectories from corresponding simulation trajectories. A gradient boosting algorithm is used for model estimation. Our study is the first-of-its-kind that uses historical function-on-function regression to demonstrate the efficacy of predicting experimental trajectories from simulation trajectories in small-scale particle manipulation under electrical fields, which eventually leads to the design of new automated processes for efficient and smart manufacturing of functional nanodevices towards next-generation neuromorphic computing.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 102 times lower power consumption compared to GPU and 103 times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

Among various phase-change memory materials (PCMs), Ge 2 Sb 2 Te 5 (GST) is an outstanding representative, widely used in both optical storage and electronic memories [1] . The intrinsic drawbacks of this GST, however, such as tellurium volatility and low amorphous phase stability (resistance retention), hinder it from being a perfect candidate. Tellurium-free antimony-based PCMs have been the subject of considerable recent interest, due to their excellent resistance contrast, rapid crystallization, and high amorphous phase stability [2] . Moreover, with increasing demand for high-capacity memory in consumer electronics, the multibit high-density storage capability of various memory devices has become very attractive [3] – [5] . Here, a bilayer Ga-Sb stack structure is demonstrated, showing multilevel switching properties. The origin of multilevel states and their stability are also studied.

In this work, we improved switching reliability with respect to memory window, switching variability and switching yield of 65nm CMOS integrated hafnium oxide (HfO2) based RRAM devices by SET/RESET process optimization. Switching performance of 1 transistor 1 RRAM (1T1R) cells as a function of operating current, SET/RESET pulse width and amplitude were investigated in depth, and full 300mm wafer scale switching optimization for the devices was demonstrated. The devices were also optimized for long cycling endurance (up to 109 cycles) and retention behavior at 373 K.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architecture offers an energy-efficient solution for DNN acceleration. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we show that the IMC system's real bottleneck is not the RRAM device but the analog-to-digital converter (ADC) precision and the stability of DNN models. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100, and ImageNet, helping understand RRAM-based IMC architectures' design limits.

Resistive random-access memory (RRAM)-based in-memory computing (IMC) architectures offer an energy-efficient solution for DNN acceleration. However, the performance of RRAM-based IMC is limited by device nonidealities, ADC precision, and algorithm properties. To address this, in this work, first, we perform statistical characterization of RRAM device variation and temporal degradation from 300mm wafers of a fully integrated CMOS/RRAM 1T1R test chip at 65nm. Through this, we build a realistic foundation to assess the robustness. Second, we develop a cross-layer simulation tool that incorporates device, circuit, architecture, and algorithm properties under a single roof for system evaluation. Finally, we propose a novel loss landscape-based DNN model selection for stability, which effectively tolerates device variations and achieves a post-mapping accuracy higher than that with 50% lower RRAM variations. We demonstrate the proposed method for different DNNs on both CIFAR-10 and CIFAR-100 datasets.

In this special session, we will reflect back on the early years of the 21st century, when much had been written about the future of engineering and engineering education. There had been global calls on changing the culture of engineering in the new century. In 2004, the National Academy of Engineering published the consensus report titled, The Engineer of 2020: Visions of Engineering in the New Century. The accompanying report came out the following year, with the title, Educating the Engineer of 2020: Adapting Engineering Education to the New Century. The first one envisioned the future, and the second one explained how we prepare for that future. As we entered the year 2020, it is now time to look back, review, and reflect: Have we met the vision of engineer 2020? This session will promote thought-provoking, reflective thinking about the past and visionary thinking about the future of engineering education.

Limitations related to the von Neumann bottleneck have resulted in novel circuits and architectures, including designs that utilize Resistive Random Access Memory (ReRAM) as nonvolatile memory (NVM) devices. ReRAM implemented with hafnium oxide (HfO 2 ) is a strong candidate for such applications. The non-volatility of these devices and their amenability to compute in memory functionality makes them ideal for neuromorphic applications, deep learning, and mathematical accelerator circuits (e.g. Vector Matrix Multiplication - VMM). However, these devices suffer from stochastic switching variability that currently limits their usage and performance. To realize the full potential of these devices, reliability analysis is required. In this work, a reliability study was performed using previously developed a 65 nm CMOS/Memristor process on a 300 mm wafer platform. To address the influence of switching compliance current on the variability of Low Resistance State (LRS) and High Resistance State (HRS), a total of 23 different compliance current values were implemented. The effects of temperature on device performance was also measured.

In this work, we have improved switching reliability of Hafnium Oxide (HfO 2 ) based CMOS integrated RRAM devices by tuning Atomic Layer Deposition (ALD) Co-reactant pulse time for HfO 2 switching layer deposition. Three different pulse times for H 2 O vapor pulses were chosen for this split: standard pulse time, 1.5X pulse time and 5X pulse time. Based on full wafer device testing results, the 5X pulse time RRAM devices showed higher mean forming voltages attributed to lower leakage current density. Additionally, 1T1R cells fabricated with 5X cycle time showed more than 2X improvement in memory window and significant reduction in HRS switching variability. We also report $\gt 95$% switching yield and a sigma of $\lt 0.5$ for cell-to-cell switching variability based on over 450 tested 1T1R devices across full 300 mm wafers, demonstrating the robustness of our process.

As CMOS scaling approaches its limitation, the power consumption of computations performed using the von Neumann architecture have become an issue. As a promising alternative solution, Resistive Random Access Memory (ReRAM) overcomes this bottleneck by enabling computationin-memory. In this work, arrays of HfO 2 -based bipolar ReRAM are simulated to carry out one such computation, called temporal correlation detection in binary processes. The correlation detection algorithm is presented, and the ReRAM model of fabricated devices was used in a Python-based simulation. The correlated and uncorrelated processes were assigned to ReRAM devices in a 5x5 array, where the ReRAM with correlated process was driven to a high conductance over time. The results show that the correlated processes are successfully detected over time.

Resistive random-access memory (RRAM) is a promising technology for in-memory computing with high storage density, fast inference, and good compatibility with CMOS. However, the mapping of a pre-trained deep neural network (DNN) model on RRAM suffers from realistic device issues, especially the variation and quantization error, resulting in a significant reduction in inference accuracy. In this work, we first extract these statistical properties from 65 nm RRAM data on 300mm wafers. The RRAM data present 10-levels in quantization and 50% variance, resulting in an accuracy drop to 31.76% and 10.49% for MNIST and CIFAR-10 datasets, respectively. Based on the experimental data, we propose a combination of machine learning algorithms and on-line adaptation to recover the accuracy with the minimum overhead. The recipe first applies Knowledge Distillation (KD) to transfer an ideal model into a student model with statistical variations and 10 levels. Furthermore, an on-line sparse adaptation (OSA) method is applied to the DNN model mapped on to the RRAM array. Using importance sampling, OSA adds a small SRAM array that is sparsely connected to the main RRAM array; only this SRAM array is updated to recover the accuracy. As demonstrated on MNIST and CIFAR-10 datasets, a 7.86% area cost is sufficient to achieve baseline accuracy for the 65 nm RRAM devices.

Detection of edges in images is an elementary operation in computer vision that can greatly benefit from an implementation with a low power-delay product. In this paper, we propose a new approach for designing nanoscale memristor crossbars that can implement approximate edge-detection using flow-based computing. Instead of the traditional Boolean approach, our methodology uses a ternary logic approach with three outcomes: True representing an edge, False that representing the absence of an edge, and Don’t Care that represents an ambivalent response. Our data-driven design approach uses a corpus of human-labeled edges in order to learn the concept of an edge in an image. A massively parallel simulated annealing search algorithm over 96 processes is used to obtain the design of the memristor crossbar for edge detection. We show that our approximate crossbar design is effective in computing edges of images on the BSD500 benchmark.

To study how though- oxide-via (TOV) induced stress affects light propagation, a numerical model is constructed using the commercially available finite element analysis (FEA) software COMSOL Multiphysics 5.4a. In the model, directional couplers are used to analyze wavelength shifts as TOV structures are placed at varying distances away. Increasing the number of TOVs in proximity to directional couplers is also explored. Finally, determining the need for a keep-out-zone is assesed for directional couplers fabricated in a silicon photonic interposer.

In this work, we have addressed cycle to cycle switching variability by modifying a key step in CMOS integrated RRAM devices fabrication, namely the atomic layer deposition (ALD) process used to deposit the HfO 2 switching layer. Two different HfO 2 ALD processes were utilized, one with an organic-based precursor, the other with a chlorine-based precursor. The trade-off between memory window (MW) and variability in the high resistance state (HRS) for RRAM cells was investigated with respect to compliance currents and reset voltages for multiple devices using both ALD precursors. The RRAM devices fabricated with the Cl-based precursor showed significant improvement in their MW/HRS resistance variability trade-off, compared to devices fabricated with the organic-based precursor over a range of compliance currents (150 μΑ to 450 μΑ) and reset voltages (−1.3V to −1.7V). Additionally, the MW shows stronger correlation with resistance variability as a function of reset voltage, mostly due to the significant change in average HRS values. To gain a statistically significant comparison, all 64 1 Transistor 1 RRAM (1T1R) cells in an 8×8 RRAM array were tested on a center die on wafers processed using both ALD precursors. Based on those 64 tested 1T1R cells, we demonstrated more than 80% switching yield for the Cl precursor HfO 2 based RRAM devices, as compared to 38% for the organic precursor devices. Additionally, 1T1R RRAM arrays fabricated using the Cl-based precursor showed more than 2× improvement in MW versus those fabricated using the organic-based precursor.