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Large arrays of nanoscale silicon field emitters are tested in a UHV system equipped with a phosphor screen. The anode current is measured and the emission pattern is captured at the same time. The emission pattern shows the whole Field Emission Arrays (FEAs) are emitting from the beginning of the test. But as the test progresses, the regions at the edge of the array are more vulnerable and tend to be damaged/shorted first. A few shorted emitters along the edges could reduce the effective gate bias applied to the central region of the array, causing the emission current of the whole array to drop dramatically, and prompt the FEA to fail, while the physical integrity of majority emitters in the array are intact.

The sputtering of Mo Spindt emitter due to the gate absorbent are observed when nA level emission current is collected by the gate for a duration of tens of seconds under a vacuum of 1×10−7 Torr.

Developments of flexible detection arrays suggest that portable robust detectors are indeed possible. A large area flexible array promises a large capture cross section in a light weight rugged format suitable for deployment at ports of entry. The approach for this detector uses a high neutron-capture cross-section layer, such as 10B, which captures incident thermal neutrons, and emits energetic ionizing charged particles. These ionizing particles are sensed using an integrated diode. The resulting charge is then amplified via a low-noise thin film transistor amplifier. We present a low-noise optimized active pixel sensor (APS) design which can be implemented in either a low temperature InGaZnO or an a-Si:H thin film transistor (TFT) process compatible with plastic substrates. Here, we also present a detectable alpha particle response with our dual stage APS design in combination with an externally connected commercial PIN diode. Furthermore, we discuss detector and array modeling which will further aid in future designs.

In this work we demonstrate that the unified model and parameter extraction method (UMEM) can be used to describe the behavior of hybrid complementary metal-oxide-semiconductor thin film transistors (CMOS TFTs) fabricated with cadmium sulfide (CdS) and pentacene as n-type and p-type active layer, respectively. Both devices were fabricated using a bottom gate configuration and top source-drain (SD) contacts. In particular, we describe the effect of semiconductor defects using the effective medium approximation, which considers a localized charge distribution in the bandgap of the semiconductor. Extracted parameters from UMEM were used in HSPICE to simulate the CMOS inverters fabricated previously by our group.

A simulation based comparative study of the polarization hysteresis of the ferroelectric capacitor using various ferroelectric models is presented. A 2-dimensional finite element device-level model was implemented using SILVACO's ATLAS device simulator to generate the polarization hysteresis characteristics for Au/Poly(vinylidene fluoride-trifluoroethylene)/Au metal-insulator-metal (MIM) device. Landau free energy expression for electric field in terms of polarization is also implemented in the MATLAB to produce the polarization hysteresis curve of polycrystalline ferroelectrics. The main drawback of these models was their inability to predict polarization saturation at the same electric field limits for which the experimental device was saturating. A new model for ferroelectric hysteresis based on curve fitting algorithm is derived that forces the polarization to be saturated at desired electric field. The MATLAB simulation of this model and the experimental hysteresis is compared which shows an excellent level of agreement.

The development of low temperature, thin film transistor processes that has enabled flexible displays also presents opportunities for flexible electronics. A variety of flexible digital and analog electronics have been demonstrated, although typically of modest performance. We review the state-of-the-art in flexible electronics followed by a discussion of the constraints, remaining challenges and realistic potential applications of thin film transistors and flexible integrated systems.

The development of flexible Complimentary Metal-Oxide-Semiconductor (CMOS) circuits reduces power consumption by ∼50x compared to n-type (or p-type) only thin film transistor (TFT) digital circuits. In this work we demonstrate a new integration approach to fabricate CMOS circuits on plastic substrates (Poly-ethylene naphthalene, PEN). We use pentacene and amorphous silicon (a-Si:H) thin film transistors for p-type and n-type devices, respectively. The maximum processing temperature for n-type TFTs is 180°C and 120°C for the p-type TFTs. CMOS circuits demonstrated include inverters, NAND and NOR gates. nMOS and pMOS carrier mobility achieved after the CMOS integration process flow are 1.0 and 0.05 cm2/V-s, respectively. Threshold voltages (V t ) are 3.89V for nMOS and −1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates are reported.

A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. Vt tuning is found to be proportional to the net dipole moment associated with the Hf-O and rare earth (RE)-O bonds at the high-k/SiO2 interface. The magnitude of this interfacial dipole moment is determined by the electronegativities and ionic radii of the RE cations. LaOx is the most effective dopant based on Vt, mobility, and reliability

We demonstrate electrical properties of rare earth (RE)-doped HfO2 and ZrO2 for application as higher permittivity (k) dielectrics in logic and memory devices. X-ray diffraction (XRD) results show that Dy, Er, and Gd doping stabilizes the higher-k tetragonal phase rather than the lower-k monoclinic phase. This preferred tetragonal phase results in a k~30. Initial electrical results show ~3 nm higher-k enables an equivalent oxide thickness (EOT) of 0.93 nm. Alternatively, ~7nm higher-k reduces leakage currents 1000x relative to HfO2 achieving

A systematic study to optimize gate stack constituents (interface, high- ?, metal gate) to maximize carrier mobility with aggressively scaled equivalent oxide thickness (EOT) is presented. We identify ultra-thin thermal oxide, atomic layer deposited HfSiON and optimized plasma nitridation performed in sequence as the optimized run path for sub-nm EOT scaling with high carrier mobility. A metal gate deposition process that minimizes the incorporation of impurities in HfSiON is also vital to maintaining good mobility at low EOTs.

We report on the relationship between the materials science of a HfO2/TiN stack and transistor performance. Atomic layer deposited (ALD) HfO2 can be scaled to a physical thickness of 1.2 nm resulting in EOT=1.0 nm. In scaling HfO2, the interfacial SiOx layer (IL) is also scaled and the extent of HfO2 crystallization is reduced. Reduced HfO2 crystallinity is coincident with reduced threshold voltage instability (10 mV) and increased electron mobility (82% Univ. SiO2). For these stable, high mobility devices, we find that HfO2 can coordinate N as Hf-N without excessive nitridation of the IL.

We demonstrate, for the first time, a HfLaSiON/metal gate stack that concurrently achieves the following: low threshold voltage (VT =0.33V), low equivalent oxide thickness (EOT=0.91nm) (Tinv =1.3nm) and 83% SiO2 mobility. Key enablers of this result are 1) La doped HfSiON for n-FET VT tuning 2) HfO2:SiO2 alloy ratio with 10% SiO2 suppressing crystallization up to 1070degC, 3) interlayer SiO2 (IL) to reduced bias temperature instability (BTI) and 4) plasma nitridation (N*)/post nitridation anneal (PNA) sequence for EOT scaling. This work advances high-k/band edge metal gate (MG) efforts by showing scalability of HfLaSiON to EOT=0.91nm without mobility or BTI tradeoff, while matching the VT of a SiO2/n-PolySi control

We show for the first time that control of the crystalline phases of HfO2 by tetravalent (Si) and trivalent (Y,Gd) dopants enables significant improvements in the capacitance equivalent thickness (CET) and leakage current in capacitors targeting deep trench (DT) DRAM applications. By applying these findings, we present a MIM capacitor meeting the requirements of the 40 nm node. A CET < 1.3 nm was achieved at the deep trench DRAM thermal budget of 1000 degC

We demonstrate that the work function of a metal gate can be varied by inserting a very thin metal layer ("metal A") between a thick metal ("metal B") and the gate dielectric. The flat band voltage (VFB) of the MOS (metal-oxide-semiconductor) capacitor structure can be controlled within the range bounded by metal A and metal B individually, as demonstrated with various stacked bi-metal layers. For continuous thin layers, we speculate that the work function tunability may be due to the drastic change of the electron density in the thin continuous metal layer in direct contact with a bulk metal. This drastic change of electron density results in a larger junction depth than that expected for a bulk metal. Non-uniform thin layers also appear effective for work function tuning as well, and the observed VFB shift is attributed to the metal island formation at the dielectric/metal A interface.

Summary form only given. Hafnium silicate (HfSi/sub x/O/sub y/) is being studied as a potential candidate material to replace SiO/sub 2/ as the gate dielectric in scaled silicon transistors due to its relatively high dielectric constant and high thermal stability. The dielectric constant of HfSi/sub x/O/sub y/ is /spl sim/8-15, depending on composition, which is 2-4 times higher than SiO/sub 2/. In this paper we describe the formation and characterization of hafnium silicate by UV/O/sub 3/ oxidation of hafnium silicide as a potential gate dielectric candidate for high performance thin-film transistors on plastic substrates.

In the molecular-beam-epitaxy growth of ternary and quaternary InGaAs and In(GaAl)As alloys on InP it is observed that the layer composition is ordered in the direction of growth. This ordering is caused by the nonuniform distribution of beam fluxes at the rotating substrate with an ordering period determined by the combined effects of growth rate and substrate rotation rate. The effect of the ordering is to produce a strained-layer superlattice whose properties can be inferred from the current-voltage characteristics of resonant-tunneling diodes. The physical and electrical characteristics of these rotation-induced superlattices are described utilizing several one-dimensional theoretical approaches to calculate the miniband structure and interpret the experimental data. >