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Your search keyword '"Bonizzoni, Edoardo"' showing total 150 results
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150 results on '"Bonizzoni, Edoardo"'

26. An Incremental-ΔΣ ADC With 106-dB DR for Reconfigurable Class-D Audio Amplifiers.

Author

Qureshi, Waqar Ahmed, Salimath, Arunkumar, Botti, Edoardo, Maloberti, Franco, and Bonizzoni, Edoardo

Abstract

This brief presents a hybrid ADC, by combining an incremental converter with a delta-sigma modulator ($\Delta \Sigma \text{M}$) to achieve a high-dynamic response, intended for audio applications. The circuit uses a ‘zero + first’-order incremental converter with a 4-b quantizer and a third-order $\Delta \Sigma \text{M}$. Combining the two binary outputs generates a 576-kHz 6-bit binary flow for directly driving a class-D amplifier. A 4-bit flash used in the incremental running at 1/16 the clock frequency and a one-shift DEM technique compensate for the capacitive mismatch and cancel its effect for input signals lower than −35 dB $_{FS}$. The proposed ADC, fabricated in a 0.18- $\mu \text{m}$ CMOS process, occupies an active area of 1.2 mm2 and consumes 7.2 mW with a 1.8-V supply. The circuit achieves an SNR/SNDR/DR of 96.8/94.45/106 dB for a 21-kHz signal bandwidth. [ABSTRACT FROM AUTHOR]

Published
2022
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27. Innovative Engineering Education in Circuits & Systems

Author

Fan, Hua, primary, Zhang, Jiayi, additional, Li, Yang, additional, Feng, Quanyuan, additional, Fang, Kaifei, additional, Wen, Hao, additional, Lin, Lishuang, additional, Qi, Xu, additional, Diao, Xiaopeng, additional, Bonizzoni, Edoardo, additional, Maloberti, Franco, additional, Ghannam, Rami, additional, and Heidari, Hadi, additional

Published
2020
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32. On the Linearity of BJT-Based Current-Mode DAC Drivers.

Author

Lupo, Nicola, Bartolini, Michele, Pulici, Paolo, Colli, Stefano, Nessi, Maurizio, and Bonizzoni, Edoardo

Abstract

This brief presents a detailed analysis on DAC-based current drivers implemented with bipolar technology. In many power applications, the need of speed and driving capability leads to the choice of bipolar transistors as driving elements, but such devices can suffer linearity issues in high accuracy applications. A method of discussion for such architectures is introduced, and the related analytical model provides a fast estimation of the linearity performances, favoring the choice of a convenient block floor-planning and an effective scrambling strategy. The theoretical computations are, then, compared with transistor level simulations results and, finally, validated by measurements, carried out on a circuit implementation manufactured in a 130-nm BiCMOS technology. [ABSTRACT FROM AUTHOR]

Published
2021
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33. A Hybrid Single-Inductor Bipolar-Output DC–DC Converter With Floating Negative Output for AMOLED Displays.

Author

Mao, Fangyu, Lu, Yan, Bonizzoni, Edoardo, Boera, Filippo, Huang, Mo, Maloberti, Franco, and Martins, Rui P.

Subjects
DC-to-DC converters, ORGANIC light emitting diodes, LIGHT emitting diodes, COMPLEMENTARY metal oxide semiconductors
Abstract

This article presents a hybrid single-inductor bipolar-output (SIBO) dc–dc converter for active-matrix organic light-emitting diode (AMOLED) displays, which are relatively more sensitive to the supply noise on the positive supply. First, to improve the display quality we adopt a floating negative output configuration to migrate all the switching ripples into the negative output, achieving a near-zero voltage ripple on the positive output. Second, we design low-power shunt regulators, which only deal with a small portion of the output ripple, to regulate the positive output voltage further, improving the load transient response. Besides, the hybrid topology and the proposed cross-coupled bootstrap-based level-shifter, with a dual-PMOS inverter buffer, only uses standard CMOS devices without deep-n-well, reducing the chip area and cost. The proposed converter, implemented in 0.35-μm CMOS with 5-V devices, operates at 1 MHz, leading to a measured positive output voltage ripple lower than 1 mV (all conditions). It achieves a measured 3-mV undershoot voltage and, an unnoticeable overshoot voltage on the positive output, when the output current varies between 30 and 350 mA. The measured peak power efficiency is 89.3% at 1.1-W output power. The maximum output power is 3.5 W. [ABSTRACT FROM AUTHOR]

Published
2021
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34. Magnetoresistive biosensors for on-chip detection and localisation of paramagnetic particles

Author

Yin, Zhaochen, Bonizzoni, Edoardo, and Heidari, Hadi

Abstract

This paper presents the design and the implementation of an on-chip magnetoresistive sensors array for cell detection and localisation. Giant magnetoresistance (GMR) sensors have been used due to their high sensitivity and resolution. A new calibration and localisation algorithm has been coded and implemented. In order to generate the required homogenous magnetic field, a custom 3D printed Hallbach cylinder has been simulated and characterised. The system includes sensory and electronic boards to collect the data and to transfer them to a computing server. The experimental results are displayed in a visual interface. Ferrofluid is used to model and simulate the magnetic field change of the cell. This paper demonstrates a 4×4 sensors array and provides a step towards the miniaturised on-chip magnetoresistive based cell detection and localisation for portable diagnostics applications.

Published
2018

39. A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications.

Author

Siddharth, R. K., Jaya Satyanarayana, Y., Nithin Kumar, Y. B., Vasantha, M. H., and Bonizzoni, Edoardo

Abstract

This brief proposes a parallel path based strong-arm latch voltage comparator. The proposed architecture improves the speed performance when compared to the conventional strong-arm latch. The improvement is achieved by the addition of parallel paths to the output node. This increases the effective transconductance at the output node, allowing the load capacitor to discharge faster during the regenerative phase. The architecture has been designed and extensively simulated at pre- and post-layout level in a 65-nm CMOS technology with a supply voltage of 1 V and it achieves a 3-GHz bandwidth. The speed increases by approximately 50% with respect to the conventional topology. The Monte-Carlo analysis is performed for 200 samples, which results in an offset standard deviation of 2.05 mV. [ABSTRACT FROM AUTHOR]

Published
2020
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40. A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery.

Author

Zeng, Wen-Liang, Bonizzoni, Edoardo, U, Chi-Wa, Lam, Chi-Seng, Sin, Sai-Weng, Chio, U.-Fat, Maloberti, Franco, and Martins, Rui Paulo

Abstract

This brief presents a successive-approximation-register (SAR) analog-to-digital converter (ADC) assisted DC-DC buck converter, which operates in discontinuous conduction mode (DCM) and achieves fast load transient recovery characteristics. The power inductor of the buck converter uses the bond-wire inductance. During the load transient, the dynamic low-power SAR ADC samples the converter’s undershoot/overshoot output voltage and controls the programmable current pump circuit to charge/discharge the output capacitor, thus speeding up and smoothing the load transient response. An additional compensation circuit is also designed to ensure the stability of the voltage mode control loop and the current pump. The chip fabricated in a 65-nm CMOS technology occupies an area of 1 mm2. The converter, switching at 100 MHz, achieves a peak power efficiency of 81% when $V_{IN}= 1.2$ V, $V_{OUT} = 1$ V and $I_{Load} = 50$ mA. When the load current steps from 2 mA to 50 mA, the measured undershoot/overshoot voltage is 101/92 mV, and the recovery time is 175/406 ns. [ABSTRACT FROM AUTHOR]

Published
2020
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41. A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma–Delta Modulator.

Author

de Aguirre, Paulo Cesar C., Bonizzoni, Edoardo, Maloberti, Franco, and Susin, Altamiro Amadeu

Abstract

This brief presents a low-voltage inverter-based continuous-time sigma-delta modulator (CT-SDM). The inverter-based amplifiers are single-stage and their operating point is provided by a bulk-based current mirror. To improve the power-efficiency, a passive RC path is used to assist the amplifier of the first integrator. The proposed modulator was fabricated in a 180-nm CMOS process with an active area of $0.36~\mathrm {mm}^{2}$. The modulator loop filter operates with a supply voltage of 0.45 V while the digital circuitry operates at 0.6 V. The modulator total power consumption is $28.72~\mu \text{W}$. For a 50-kHz signal bandwidth, the measured peak SNR/SNDR is 71.24/70.64 dB and the achieved DR is 78.3 dB, leading to a Schreier figure-of-merit of 170.70 dB. [ABSTRACT FROM AUTHOR]

Published
2020
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