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A low-temperature fabrication of Al x Ga1–xN/GaN MISHEMTs on a 200-mm GaN-on-Si substrate using a common metal stack (Ti/Al/NiV) for concurrent source, drain, and gate formation is demonstrated. An ohmic contact resistance of 0.8 \Omega -mm and a specific contact resistivity of 6\times 10^\mathrm -6 \Omega -cm2 are achieved at an annealing temperature of 500 °C. The fabricated MISHEMTs have excellent electrical characteristics: an I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} ratio of nine decades (due to subnanoampere off-state leakage current up to a −15 V gate bias), and a subthreshold swing of 80 mV/decade (by virtue of a relatively low Al0.23Ga0.77N/GaN interface-trap density on the order of 10^11 cm ^\mathrm -2 eV ^\mathrm -1 ). The demonstrated approach is thus a promising alternative toward the gold-free GaN-on-Si integration. [ABSTRACT FROM AUTHOR]

For the first time, the random telegraph signal (RTS) and its corresponding flicker noise (1/ƒ) were investigated in gate-all-around p-type Si-FinFETs. For a device with gate width of ∼ 100 nm (fin height) and length of ∼ 200 nm, the typical RTS capture/emission time constants were ∼ 0.1-1 ms. Very large RTS amplitudes (ΔId/Id up to 25%) were observed, which is an effect attributable to the extreme device scaling and/or interface quality of FinFETs. The estimated scattering coefficients (α ∼ 10-12 - 10-13) are found to be higher than typical values obtained from MOSFETs. These findings demonstrate the relevance of RTS for FinFET operation. [ABSTRACT FROM AUTHOR]

This letter reports on a device layer transfer (based on thermal bonding and grinding backside Si) process and device characteristics of Si MOSFETs on a flexible substrate, focusing mainly on the mechanical bendability of the device and resistance to fatigue. The results demonstrated a well-optimized bonding process, as indicated by the nearly indiscernible performance difference (e.g., subthreshold slope, Vth, and Idsat) before and after the bonding of Si with the flexible substrate. The device characteristics indicate excellent bendability of Si MOSFETs on flexible substrate (e.g., for radius tested down to ±72 mm) and good immunity to fatigue (e.g., negligible performance drift tested up to 103 bending cycles with a radius of ±126 mm). Results suggest the feasibility of this approach in achieving high-performance MOSFETs for applications in performance-sensitive and flexible electronics. [ABSTRACT FROM AUTHOR]

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SO!) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (ϵ ∼ -1.07%) strained-Si0.55Ge0.45 and the n-MOSFET in tensile-strained Si over the relaxed Si0.80Ge0.20 exhibited significant hole (enhancement factor ∼ 1.9) and electron (enhancement factor ∼ 1.6) mobility enhancements over the Si reference. [ABSTRACT FROM AUTHOR]

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with ≤5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (∼ 63 mV/dec), low drain-induced barrier lowering (∼ 10 mV/V), and with ION/IOFF ratio of ∼ 106. High drive currents of ∼ 1.5 and ∼ 1.0 mA/μm were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body. [ABSTRACT FROM AUTHOR]

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (∼0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average ΔId/Id ∼ 10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (Lg ∼ 55 nm -0.530 μm/W ∼2-20 μm). The p-MOSFETs also Exhibited Id-improvement by ∼7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, the fabrication of vertically stacked SiGe nanowire (NW) arrays with a fully CMOS compatible technique. Our method uses the phenomenon of Ge condensation onto Si and the faster oxidation rate of SiGe than Si to realize the vertical stacking of NWs. Gate-all-around n- and p-FETs, fabricated using these stacked NW arrays as the channel (Lg ≥ 0.35 μm), exhibit excellent device performance with high ION/IOFF ratio (∼106), near ideal subthreshold slope (∼62–75 mV/dec) and low drain induced barrier-lowering (∼20 mV/V). The transconductance characteristics suggest quantum confinement of holes in the [Ge]-rich outer-surface of SiGe for p-FETs and confinement of electrons in the core Si with significantly less [Ge] for n-FETs. The presented device architecture can be a promising option to overcome the low drive current restriction of Si NW MOSFETs for a given planar estate. [ABSTRACT FROM AUTHOR]

A gate-first self-aligned Ge nMOSFET with a metal gate and CVD HfO2 has been successfully fabricated using KrF laser annealing (LA) as dopant-activation annealing. By applying an aluminum laser reflector on TaN metal gate, source/drain (S/D) regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. As a result, a larger drive current and a lower threshold voltage are achieved in Ge nMOSFET using LA activation than that using conventional rapid thermal annealing activation. [ABSTRACT FROM AUTHOR]

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (∼1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO2, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800 °C-1000 °C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000 °C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000 °C. [ABSTRACT FROM AUTHOR]

A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-µm gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The n+-p junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in OFF-state leakage (~5 ×) and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors. [ABSTRACT FROM AUTHOR]