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155 results on '"Bender, H."'

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1. Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-Cap-Free Gate Stack and Optimizing the Channel Strain

2. Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits

4. 3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors

5. Non-filamentary (VMCO) memory : a two- and three-dimensional study on switching and failure modes

6. Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET

7. First demonstration of vertically-stacked Gate-All-Around highly-strained Germanium nanowire p-FETs

8. An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

9. Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration

10. Non-filamentary (VMCO) memory: A two-and three-dimensional study on switching and failure modes

11. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates

12. Si-passivated Ge nMOS gate stack with low Dit and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

13. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

14. Top-down InGaAs nanowire and fin vertical FETs with record performance

15. Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

16. Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability

17. First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs.

18. Ge nFET with high electron mobility and superior PBTI reliability enabled by monolayer-Si surface passivation and La-induced interface dipole formation

20. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

21. Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

22. Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS

24. First demonstration of 15nm-WFIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

25. Performance and reliability of high-mobility Si0.55Ge0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

26. 15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

27. An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

30. Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM): An area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window resistive switching cell

31. Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

34. Stress simulations for optimal mobility group IV p- and nMOS FinFETs for the 14 nm node and beyond

35. Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

36. Towards high mobility GeSn channel nMOSFETs: Improved surface passivation using novel ozone oxidation method

38. Towards the Monolithic Integration of III-V Compound Semiconductors on Si: Selective Area Growth in High Aspect Ratio Structures vs. Strain Relaxed Buffer-Mediated Epitaxy

39. Process control & integration options of RMG technology for aggressively scaled devices

41. Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration

42. High performance Si.45Ge.55 Implant Free Quantum Well FET featuring low temperature process, eSiGe stressor and transversal strain relaxation

43. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation

44. Record low contact resistivity to n-type Ge for CMOS and memory applications

45. Investigation of rare-earth aluminates as alternative trapping materials in Flash memories

46. High-mobility Si1−xGex-channel PFETs: Layout dependence and enhanced scalability, demonstrating 90% performance boost at narrow widths

47. 8Å Tinv gate-first dual channel technology achieving low-Vt high performance CMOS

48. Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

49. Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

50. 0.5 nm EOT low leakage ALD SrTiO3 on TiN MIM capacitors for DRAM applications

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