Search

We propose logic gates and circuits implemented with 2-D charge density wave (CDW) devices, which operate at room temperature. The 1T-TaS2 charge density wave devices exhibit a voltage triggered phase transition between the nearly commensurate and incommensurate CDW states, which is accompanied by an abrupt change of the resistance and hysteresis. The unique output characteristics of such devices allow for building logic gates and circuits without any transistors. Using the experimentally measured current–voltage characteristics, we model and numerically simulate the performance of the inverter and the OR logic gates consisting of CDW devices and regular resistors. Owing to the radiation-hard nature of the CDW devices and absence of transistors, the proposed circuits can be utilized in various harsh environments on earth or outer space. [ABSTRACT FROM AUTHOR]

We propose an oscillatory neural network implemented with two-dimensional (2-D) tantalum disulfide devices operating in the change density wave regime at room temperature. An elementary cell of the network consists of two 1T-TaS2 devices connected in series. Such a cell has a constant output and oscillatory states. All cells have the same bias voltage. There is a constant current flowing through the cell in the constant output mode. The oscillations occur at a certain bias voltage due to the electrical-field triggered metal-to-insulator transition owing to the changes in the charge-density-wave phase in the 1T-TaS2 channel. Two 1T-TaS2 devices oscillate out-of-phase when one of the devices is in the insulator phase while the other one is in the metallic state. The nearest-neighbor cells are coupled via graphene transistors. The cells are resistively coupled if the graphene transistor is in the on state while they are capacitively coupled if the transistor is in the off state. The operation of the oscillatory neural network is simulated numerically for the 30 × 30 node network. We present the examples of pattern recognition on a template with the fixed coupling among the near-neighbor cells. We also present the results of our numerical modeling mimicking the Game of Life in the network with the time-varying coupling. The 2-D 1T-TaS 2 devices, utilized in the network, offer a unique combination of properties such as scalability, high operational frequency, fast synchronization speed, and radiation hardness, which makes them promising for both consumer electronic and defense applications. [ABSTRACT FROM PUBLISHER]

Variability effects in graphene can result from the surrounding environment and the graphene material itself, which form a critical issue in examining the feasibility of graphene devices for large-scale production. From the reliability and yield perspective, these variabilities cause fluctuations in the device performance, which should be minimized via device engineering. From the metrology perspective, however, the variability effects can function as novel probing mechanisms, in which the “signal fluctuations” can be useful for potential sensing applications. This paper presents an overview of the variability effects in graphene, with emphasis on their challenges and opportunities for device engineering and applications. The discussion can extend to other thin-film, nanowire, and nanotube devices with similar variability issues, forming general interest in evaluating the promise of emerging technologies. [ABSTRACT FROM PUBLISHER]

The controlled modification of graphene properties is essential for its proposed electronic applications. Here, we describe a possibility of tuning electrical properties of graphene via electron-beam (e-beam) irradiation. We show that by controlling the irradiation dose one can change the carrier mobility and increase the resistance at the minimum conduction point in the single layer graphene. The bilayer graphene is less susceptible to the e-beam irradiation. The modification of graphene properties via irradiation can be monitored and quantified by the changes in the disorder D peak in Raman spectrum of graphene. The obtained results may lead to a new method of defect engineering of graphene physical properties. They are also important implications for fabrication of graphene nanodevices, which involve scanning electron microscopy and e-beam lithography. [ABSTRACT FROM PUBLISHER]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

We report on the transport and low-frequency noise measurements of MoS2 thin-film transistors (TFTs) with thin (2–3 atomic layers) and thick (15–18 atomic layers) channels. The back-gated transistors made with the relatively thick MoS2 channels have advantages of the higher electron mobility and lower noise level. The normalized noise spectral density of the low-frequency 1/ $f$ noise in thick MoS2 transistors is of the same level as that in graphene. The MoS2 transistors with the atomically thin channels have substantially higher noise levels. It was established that, unlike in graphene devices, the noise characteristics of MoS2 transistors with thick channels (15–18 atomic planes) could be described by the McWhorter model. Our results indicate that the channel thickness optimization is crucial for practical applications of MoS2 TFTs. [ABSTRACT FROM AUTHOR]

We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of -7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude. [ABSTRACT FROM AUTHOR]

Graphene was recently proposed as a material for heat removal owing to its extremely high thermal conductivity. We simulated heat propagation in silicon-on-insulator (SOI) circuits with and without graphene lateral heat spreaders. Numerical solutions of the heat-propagation equations were obtained using the finite-element method. The analysis was focused on the prototype SO! circuits with the metal-oxide-semiconductor field-effect transistors. It was found that the incorporation of graphene or few-layer graphene (FLG) layers with proper heat sinks can substantially lower the temperature of the localized hot spots. The maximum temperature in the transistor channels was studied as function of graphene's thermal conductivity and the thickness of FLG. The developed model and obtained results are important for the design of graphene heat spreaders and interconnects. [ABSTRACT FROM AUTHOR]

We present results of the experimental investigation of the low-frequency noise in bilayer graphene transistors. The back-gated devices were fabricated using the electron beam lithography and evaporation. The charge neutrality point for the transistors was around +10 V. The noise spectra at frequencies f > 10-100 Hz were of the 1/f type with the spectral density on the order of SI ∼ 10-23-10-22 A2/Hz at the frequency of 1 kHz. The deviation from the 1/f spectrum at f < 10-100 Hz suggests that the noise is of the carrier-number fluctuation origin due to the carrier trapping by defects. The Hooge parameter was determined to be as low as ∼10-4. The gate dependence of the normalized noise spectral density indicates that it is dominated by the contributions from the ungated parts of the device and can be reduced even further. The obtained results are important for graphene electronic and sensor applications. [ABSTRACT FROM AUTHOR]

It is well recognized that power consumption and heat removal in state-of-the-art integrated circuits (ICs) with the nanometer size of transistors is an urgent challenge. The electronic industry's transition to multicore designs, where the performance increase is achieved not via the increase in the clock frequency but rather through the increase in the number of processors, helped to alleviate some of the thermal issues but has not solved the problem of the nonuniformity of heat distribution inside a computer chip. [ABSTRACT FROM PUBLISHER]