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Hardware inefficiency of neural synapse multiplication has placed an upper limit on the neural network size that can be implemented on a single FPGA. In this paper, we make use of distributed arithmetic and internal lookup tables of FPGA structures to improve the efficiency of synapse multiplication. We propose a weight clustering optimization method to further reduce area requirements of the target hardware. Applying our proposed method to a sample neuron, we were able to reduce the hardware requirements of synapse multiplier by 30%. Our parameterized approach can be utilized for automation of neural network synthesis onto FPGA devices.

Steady FPGA density and speed improvement in recent years has paved the path for realization of larger Neural Networks On a Programmable Chip (NNOPC), a high performance and low cost alternative to traditional physical implementations of artificial neural networks. In this paper, we propose a parametric approach for mapping artificial neural networks onto FPGA structures, as well as an optimization method to reduce area requirements of the synthesized hardware. Applying this method to a sample neuron, we achieved a 30% reduction in hardware resource requirements of the synaptic multiplier.