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This work examines the design of high Q-factor inductor for LC voltage-controlled oscillator (VCO) in TSMC 0.18μm n-well CMOS process technology and 1.5 V supply voltage. The planar structure of graphene and its sufficient relation time make it easier to pattern graphene into helical structures without additional contacts at each corner. The inductor is modelled with the widely accepted π-mudel and the results show that graphene inductor achieves a high Q-factor with reduced parasitics and losses when compared with Cu wire inductor. Following this, we employed the inductor in the design of 2 GHz LC VCO. From the Cadence/Spectre simulations, we obtained that the tuning range of voltage-controlled oscillator is 1.62 GHz to 3.93 GHz and the phase noise measured is -124.8 dBc/Hz at 1 MHz offset frequency. In addition, the VCO has a figure of merit (FoM) of206.4 dBc/Hz and consumes 3.66 mW power.

With the steady advancement of human civilization, energy lack and ecological contamination have become an ever-increasing number of critical difficulties in our reality, and they are issues that should be settled desperately. Perovskite, a potential material for sustainable ideal energy source, boundless, and clean energy. Perovskite with general formula ABX3 plays an important role in electrode and electrolyte for solar cells which is most ideal alternatives to silicon solar cells, supercapacitor, Bio fuel and solid oxide fuel etc. because of their stability, ferroelectric, supreme, catalytic, dielectric and high charge carrier mobility. In this paper the perovskite doped with rare earth Gd and Nd was synthesise by a solid reaction technique at high temperature. XRD confirms the tetragonal structure of single step. Dielectric behaviour of PVSK ceramics was studied using CIS technique within range of 9000C to 12500C and frequency range of 1 kHz and 1 MHz the existence of the ac conductivity variance indicates the electrical conductivity form of Arrhenius. The dielectric constant of the materials is very high which is needed for the energy storage device. The material's tangent loss is very low until the transition temperature is very high. The tolerance factor of PVSK material was found to be nearly 1.

This work presents the implementation of analytical transport model of M o S 2 tunnel field effect transistor (TFET) using Verilog-A in Cadence/Spectre. The parameters of the model are extracted, and most notable is its high I ON /I OFF ratio, which makes it suitable for low power design, and IoT applications. Subsequently, we employ the TFET model in the design of ultralow power phase locked loop (PLL). Various components of PLL are examined in terms of their structures and functions. The results show that the voltage controlled oscillator (VCO) operates from 0.5 GHz to 2.9 GHz with a tuning range of 82.8%. It also consumes 1.91 μW power at 2 GHz carrier and has a phase noise of -117.3 dBc/Hz at 1 MHz offset frequency. The average power consumed by phase locked loop is 0.021 mW. In addition, the operation of the PLL is not sensitive to temperature variations.

There are limitations in CMOS transistor as the technology scales down. The problem of short channel effects (SCE) has become dominant, which causes the malfunction and failure of CMOS circuits. Various devices are proposed to continue extending Moore's law and the roadmap in semiconductor industry. Memristor is a two terminal passive device, which has proven to be compatible with MOSFET microfabrication processes and also offers some distinctive features. It is a nano-dimensional device, so it saves a lot of die area and consumes less power. Similarly, FinFET structure has aided in better electrostatic control of transistor channel. The leakage current and power are reduced, thus, it shows better performance than MOS transistor. FinFET exhibits temperature effect inversion (TEI) because its I ON increases even at the superthreshold region. The integration of graphene nanoribbon (GNR) FET into IC design has shown a lot of improvements in terms of speed and power. In this work, we present the characteristics of GNRFET and design an inverter circuit using Cadence/Spectre. Following this, a three-stage ring oscillator (RO) is designed, and the results show that its center frequency is 30.2 GHz with a phase noise of −125.2dBc/Hz. In addition, it consumes 0.15 mW power, which makes it suitable for high frequency and low power applications. More so, the RO has a very good phase noise performance.

There are tremendous improvements in performance of transistor in CMOS technology by scaling down its size. However, there are various challenges, such as short channel effects (SCE), that are associated with miniaturization. FinFET technology is a promising technique to overcome these issues because it offers better electrostatic control of the channel than planar CMOS transistor as the technology scales down. In this work, we have proposed a phase locked loop (PLL) design with FinFET and memristor. The resistive and capacitive (R-C) components of loop filter are replaced with memristor and memcapacitor, respectively, in order to minimize the die area and reduce power consumption. The designed PLL produces a tuning range of 0.25 - 1.60 GHz at center frequency of 1 GHz with 2.05 mW average power consumption. The voltage-controlled oscillator (VCO), which contributes majorly to the total phase noise in phase locked loop, has a phase noise -135.2 dBc/Hz at 1 MHz offset frequency. In addition, the PLL shows high reliability with wide variations in temperature.

Adiabatic logic families typically use signal waveforms very different to standard static CMOS logic. Pulsed power-clocks driving the circuit lead to pulsed or sinusoidal signals that cannot be easily interfaced with existing CMOS logic structures. This work focuses on a novel interface circuit that converts existing signals in ECRL (efficient charge recovery logic) to signals typical of standard CMOS logic. Energy losses are evaluated based on switching speed and the nature of the incoming bitstream to the interface. Comparison to an existing reference interface is included, weighing the advantages and disadvantages inherent to both interfaces. All circuits were designed, extracted, and simulated in 180nm CMOS technology. The proposed interface effects energy savings in unique conditions when compared to the reference work and exploits unique properties of the adiabatic logic signaling for proper functionality.

We report, for the first-time pressure-less synthesis of 2D diamond thin film from graphene on a copper foil using cold wall CVD. Continuous hydrogenation of multilayer graphene on a copper substrate results in stable phase transition of graphene to optically visible diamond thin film on the copper foil. Characteristic sp3 C-C bond in X-ray photoelectron spectroscopy and Raman characteristic diamond peak at 1332 cm-1 confirm the material as 2D diamond thin film.

We present review of the current transport behavior of silicene field effect transistor (FET) in which a monolayer of honeycomb lattice made of silicon is used as $a$ transport channel. Based on this study, we introduce a SPICE-compatible model of the silicene FET. The proposed model is characterized by the channel dimension, temperature and externally applied voltage. In addition, vacancy defects in silicene material are also considered for current transport analysis. We have demonstrated application of our developed model for the design of an amplifier circuit. It is observed that silicene FET based amplifier can be powered by 0.4V with nearly 25dB gain and 200MHz unit gain bandwidth. We also designed an active integrator and frequency doubler using the silicene FFT-based amplifier and simulated. Our results demonstrate that the proposed SPICE-compatible silicene FET model can be used for very low-power and medium-to-Iow frequency analog circuit designs.

In this paper, four different power-clock gating schemes for use with four-phase adiabatic logic were evaluated and compared with respect to idle power reduction and active power consumption increase. Specifically, single buffer/inverter structures implemented in efficient charge recovery logic (ECRL) were used to generate the simulation data. Separate header and footer power-gating schemes were considered as well as standard digital control signals and pulsed adiabatic logic style control signals. All simulation data was generated using Tanner’s T-SPICE software and 180nm CMOS technology.

A numerical simulation based on self-consistent solution of non-equilibrium Green's function (NEGF) formulism and Poisson equation has been developed in order to investigate the width-dependent characteristics of GNR FETs in two GNR families (3p,0) and (3p+1,0). On-state characteristics such as transfer characteristics, transconductance, gate capacitance, intrinsic cut-off frequency and intrinsic gate-delay time have been studied. We found that while the maximum intrinsic cut-off frequency of both GNR families are increased by increasing the GNR width, GNR(3p,0) shows superior performance such as more than twice larger intrinsic cut-off frequency at lower gate voltages, higher drive current and lower intrinsic gate-delay time, indicating GNR(3p,0) a more preferable attribute than GNR(3p+1,0) for high frequency applications.

Performance of graphene nanoribbon (GNR) tunnel field effect transistor (TFET) has been modeled in Verilog-Analog (Verilog-A) using previously reported physics based compact analytical current transport model. Performance obtained using both analytical model and Verilog-A simulations are compared providing excellent match. Using n-type and p-type GNR TFETs, inverter circuit is designed and simulated in Mentor Graphics® Tanner EDA S-Edit and T-Spice utilizing the developed Verilog-A codes. With suitable choice of supply voltage, our Verilog-A simulated GNR TFET inverter provides low propagation delay, low power dissipation and retains strong signal integrity.

Low power and robust circuitry are permanent hots pots in VLSI design. Adiabatic logic is one of potential breakthroughs for these goals. Especially, designing reliable clock tree is very significant for adiabatic logic due to four-phase clocked power required for pipelined data transmission in adiabatic system. In this paper, we present analysis of charging speed and clock types that influence power dissipation in adiabatic logic and comparison of current mainstream clock generators suitable for adiabatic system. Based on the characteristics of current designs, using TSMC 180nm fabrication process, we propose a novel mixed clock generator, including four-phase source, switch controller and clock MUX to build a robust clock using only one reference clock. The test shows that below 600MHz, the proposed design has negligible signal attenuation with low power dissipation. We have also compared our work and current designs in device cost, and suitable work frequency based on circuit structure.

In this paper, graphene nanoribbon field effect transistors (GNR FET) have been used in design of new energy-efficient XNOR/XOR gates based on clocked adiabatic logic (CAL), which results in the reduction of power density by nearly 65% comparing with the earlier CAL design in 45 nm technology node. In addition, the GNR FET allows scaling of supply voltage, which results in nearly three times reduction in power density. The on-chip power density of new XNOR/XOR gates remains below the limit reported by the International Technology Roadmap for Semiconductors (ITRS) up to the operation frequency of about 1GHz at the scaled supply voltage equal to 0.7V.

Transistor scaling and voltage scaling promote the development of VLSI chip design and modern portable devices. However, transistor scaling brings dark silicon to chips. Lowering supply voltage also results in many transistors to work in near threshold voltage region in which transistors are very sensitive to voltage variation. The paper analyzes the influence of IR drop in a chip multiprocessor (CMP) architecture. Based on our previous work, we focus on the circuit implementation of the proposed switch able pin in CMP using I/O pads with on-chip low cost control circuit, and to let the microprocessor work in data mode or power mode according to various requirements. Using six of eight traditional data pins in an 8-bit RISC microprocessor as switch able pins, the entire current in power mode can be boosted by 72% compared to normal data mode. For data transmission, relative signal-to-noise ratio (rSNR) are tested and the performance of the DRAM is also discussed.

Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to keep pace with higher density of transistors and high performance. For appropriate trade-offs between performance and limitation of power dissipation, dark silicon has appeared in the current processors. With the number of transistors increasing in future chips, we could envision that next generation processors might be getting darker and darker. This compromise could reduce multiple-core processors' efficiency. In this paper, power dissipation and circuit optimization are discussed in an attempt to mitigate dark silicon for future processors. A power monitor and its algorithm are proposed mainly to explain how to efficiently regulate voltage and power in the future processors with multiple cores.

Performance of multiwall carbon nanotube (MWCNT)-based VLSI interconnect has been studied under the strong influence of scattering induced by self-heating. Using modified Landauer Buttiker formalism along with Fourier heat transfer equation we have estimated interconnect parameters at different diameters. Anisotropic thermal conductivity has been considered for temperature distribution calculation using FDTD method for primitive defect-less MWCNT. Using the relaxation time approximation, we have studied scattering dynamics in calculating resistance. Electronic and thermal transport equations have been coupled and solved iteratively to get accurate estimation of temperatures and resistances. Total intrinsic resistance has been estimated as low as 16 Ω for a MWCNT of 100 nm outer diameter. Even though temperature gradient has been calculated as high as 6000K/m the most hot spot has been estimated only 0.0035K higher than the surroundings, which is not enough temperature to reach melting point. Study of scattering parameters confirmed the higher bandwidth with low transmission loss (10 THz within -20dB limit) is achievable for MWCNTs with more shells (D>50 nm).

In this work, we present a novel structure of Graphene NanoRibbon Field-Effect Transistor (GNR FET) to reduce short channel effects. In this structure, two side metal gates with lower work-function than the main gate are used in a conventional double-gate (DG) GNR FET topology to provide virtual extensions to source/drain regions while these are biased constant, independent of the main gate. The proposed GNR FET structure improves drain-induced barrier lowering (DIBL), which can reduce the short-channel effects (SCE) in device performance such as on/off current ratio, off-state current and subthreshold slope to make it a more suitable configuration than the normal GNR FET for digital integrated circuit design.

In this work, an analytical current transport model of Graphene Nanoribbon (GNR) Tunnel Field Effect Transistor (T-FET) is presented considering drain source voltage (VDS), gate source voltage (VGS), carrier mobility (μ) and top gate dielectric (tOX). For a GNR width of 5nm at 0.275eV band gap, ON current of 1605 μA/μm is calculated with a very high ON/OFF current ratio of 107. Subthreshold slope of 7.07mV/decade is calculated from I-VGS transfer characteristics. Current saturation is observed for input voltage, VGS of 0.28V and beyond for varying VDS values. Performance of the proposed model is compared with the earlier published work and the projected 2011 ITRS MOSFET requirements and it is found that considering proper device geometry and input voltages, GNR T-FET can demonstrate seven times lower power dissipation and eight times higher intrinsic speed in the upper GHz range than in conventional CMOS technology.

In this work, we present testing of trusted CMOS data converters using DeltaIDDQ and on-chip linear ramp histogram techniques. DeltaIDDQ technique can be efficiently used to detect faults taking process variation into effect. We present design for an on-chip testability of CMOS analog-to-digital converter using linear-ramp histogram technique. The paper discusses a brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5µm n-well CMOS process, the results and effectiveness of the design. The on-chip linear ramp histogram technique can be seamlessly combined with DeltaIDDQ technique for improved testability, increased fault coverage and reliable operation.

A new CMOS LC voltage-controlled oscillator (VCO) circuit design using multiwalled carbon nanotube (MWCNT) wire inductor in LC tank circuit is presented. The VCO is designed in TSMC 0.18 μm CMOS process. We have applied our recently reported one-dimensional fluid electronic transport model of multiwalled carbon nanotube interconnect in π-model of the inductor. We have studied the oscillation frequency and phase noise of CMOS LC VCO and compared the performance using MWCNT and Cu wire inductors as a function of the quality factor (Q). We have shown that the oscillation frequency of the CMOS LC VCO is increased due to high-Q of MWCNT wire inductor. We have also shown that the phase noise performance of VCO designed with MWCNT wire inductor is also considerably improved in comparison to that of VCO designed with conventional Cu wire inductor.

In this paper, utilization of energy recovery techniques in carbon nanotube field-effect transistor (CNT-FET) circuits is discussed. Four different energy recovery techniques for complementary on-chip CNT-FET XNOR/XOR circuits are extensively studied and simulated using Cadence® Spectre simulator. The simulation results show that the power density of CNT-FET circuits is much higher than the maximum power density limit set by ITRS 2003. Among the four energy recovery circuits, new clocked adiabatic logic (CAL) type CNT-FET circuits exhibit the best performance.

We present, implementation of a built-in current sensor (BICS) which takes into account the increased background current of defect-free circuits and the effects of process variation on ?IDDQ testing of CMOS data converters. A 12-bit digital-to-analog converter (DAC) is designed as the circuit under test (CUT). The BICS uses frequency as the output for fault detection in CUT. A fault is detected if it causes the output frequency to deviate more than ±10% from the reference frequency. The output frequencies of the BICS for various (MOSIS) model parameters are simulated to check for the effect of process variation on the frequency deviation. A set of eight faults simulating manufacturing defects in CMOS data converters are injected using fault-injection transistors and tested successfully.

Two CMOS phase-locked loop chips are designed and fabricated in 0.5 µm n-well CMOS process using single-ended voltage-controlled oscillator and differential voltage-controlled oscillator circuits. Hot carrier effects, jitter and phase noise performances are investigated and analyzed. On-chip measured experimental results show that for the phaselocked loop with the single-ended voltage-controlled oscillator working at 500 MHz carrier frequency, phase noise is −76 dBc/Hz at 10 kHz offset frequency and −119 dBc/Hz at 1 MHz offset frequency. For the phase-locked loop with differential voltage-controlled oscillator working at 500 MHz, phase noise reaches −82 dBc/Hz at 1 kHz offset frequency and −122 dBc/Hz at 1 MHz offset frequency. Tuning frequencies of the two phase-locked loops decrease about 100–200 MHz when subjected to four hours of hot carrier stress. The single-ended VCO gain decreases from 260 MHz to 70 MHz due to hot carrier stress. For the phase-locked loop with the differential voltage-controlled oscillator, a 50 ps RMS jitter increase is observed under hot carrier stress.

In this paper, we propose a circuit model of the multi-walled carbon nanotube (MWCNT) based on our one-dimensional fluid model, which describes the electron transport in single-walled carbon nanotube (SWCNT). The performances of MWCNT and SWCNT in high frequency (RF/microwave) applications are then simulated using these models and compared with Cu interconnect. Simulations show that MWCNT interconnects can potentially have higher transmission efficiency and lower reflection losses than that of SWCNTs and Cu interconnects.

Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

Using derived equations for the potential description for carbon nanotube field effect transistors (CNT-FETs), basic semiconductor equations for carbon nanotubes have been used to model the charge transport. The carbon nanotube has been modeled as a line of charge, and a numerical model has been implemented for the current transport. This numerical model uses MATLAB capabilities to solve the given current and voltage equations numerically and presents I-V characteristics for any given CNT-FET.

In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.

In this paper, we propose a two-port network model of a single walled (SW) carbon nanotube field effect transistor (CNT-FET) which includes contacts for analyzing S-parameter measurement results. The radio frequency (RF) transmission properties of single walled CNT-FETs have been characterized up to 12 GHz using the proposed two-port network model. The analytical results are in good agreement with the published experimental results.

The loop model of a second order phase-locked loop (PLL) is presented. The effects of different building blocks on the phase noise performance of PLLs are analyzed. Input reference clock, voltage-controlled oscillator (VCO) and the frequency divider are the dominant noise sources in a PLL system. PLL phase noise prediction by the graphical treatment is introduced. Different types of VCOs are fabricated in 0.5mum CMOS process to investigate the open loop VCO noise. PLLs with different VCOs are also fabricated to study the effect of VCO noise, input reference noise and the divider noise on the noise performance of the whole PLL system. Experimental results closely follow the predicted performance.

We present design, implementation and test of a built-in current sensor for Delta-IDDQ testing of a CMOS 12-bit charge scaling digital-to-analog converter (DAC). The sensor uses power discharge method for the fault detection. The integrated sensor and the DAC on a chip have been designed and implemented in a 0.5 mum n-well CMOS technology. The DAC uses charge scaling method for the design and a low voltage (0 to 2.5 V) folded cascode op-amp. The built-in current sensor (BICS) has a resolution of 0.5 muA. Faults have been introduced into the DAC using fault injection transistors (FITs). Fault detection by the BICS has been verified both from simulation and experimental measurements.

Phase noise may be regarded as the most severe cause of performance degradation in OFDM systems. Hot-carriers (HCs), found in the CMOS synchronization circuits, are high- mobility charge carriers that degrade the MOSFET devices' performance by increasing the threshold voltage required to operate the MOSFETs. The HC effect manifests itself as the phase noise, which increases with the continued MOSFET operation and results in the performance degradation of the Voltage-Controlled Oscillator (VCO) built on the MOSFET. The HC effect is particularly evident in the short-channel MOSFET devices. The MOSFET instability will impact on the OFDM system performance. The relationship between the OFDM system performance and the hot-carrier effect can be analyzed in terms of a crucial parameter, the threshold voltage. In this paper, we adopt the phase noise model for double-ended ring oscillators, and derive a sensitivity function which can provide insights into the expected OFDM system performance for the system design engineers. The expected OFDM performance degradation due to the hot carrier effect is also provided through our simulations.

Phase noise is a critical factor that degrades the synchronization performance of a wireless communication receiver. Hot-carriers (HCs), found in the CMOS synchronization devices, are high-energy charge-carriers that can degrade the MOSFET's performance by damaging the internal structure and lead to an increase in the phase noise therein. The increase in the phase noise can be related to a critical parameter, the MOSFET threshold voltage. The HC effect is particularly evident in the short-channel MOSFET devices. In this paper, we analyze the impact of the phase noise arising from the HC effect on the single-carrier QAM systems in terms of the symbol-error-rate (SER) and the signal-to-interference-plus-noise ratio (SINR). We provide an exact analysis for the SER and SINR degradation for the QPSK systems in the presence of the phase noise, and verify our analytical results through computer simulations. In addition, we illustrate the performance degradation of the single-carrier 16-QAM and 64-QAM systems via Monte Carlo simulations. Through our analysis and simulations, we can show that the SER performance of the QPSK systems can deteriorate by two orders-of-magnitude at an SNR of 10 dB. Our analysis can help the design of receivers for single-carrier wireless systems built on short-channel MOSFET devices

In this paper, an oversampling sigma-delta analog-to-digital converter (ADC) has been designed and implemented in 1.5 mum n-well CMOS process using a 1st order modulator and a 2nd order cascaded integrator comb (CIC) decimation filter. The modulator, which is the analog part of the ADC, has been designed using floating gate MOSFETs, which offers a higher common mode range for analog signals. The decimation filter is a digital low pass filter and can be programmed to give 7-bit and 10-bit digital outputs depending upon the oversampling ratio of 16 and 64, respectively. The ADC can be operated up to a clock sampling frequency of 8 MHz

In this paper, the hot-electron-induced degradation in voltage-controlled oscillator (VCO) is investigated. A current starved VCO is designed in 0.25 mum CMOS process to verify the VCO gain degradation due to hot-carrier effects. The loop dynamics, phase noise and output clock jitter of a second order PLL are studied. The loop parameters, i.e., damping factor and natural frequency, phase noise and jitter degradations due to VCO degradation are analyzed, considering hot-carrier effects. After four hours stress, there is a 23% decrease in the damping factor and natural frequency, also 1 dB increase in phase noise and 17% increase in output RMS jitter

A new built-in current sensor (BICS) has been proposed in this paper for the detection of open and short faults. The BICS compares the quiescent current from the circuit under test (CUT) with the reference current. If a fault is detected it gives /spl plusmn/2.5 V at the output depending on the nature of defect. A two stage CMOS op-amp, 3 bit flash architecture based ADC, 3 bit charge scaling architecture based DAC have been used as the CUT. The faults in the circuits have been introduced using fault injection transistors (FITs). A combination of nine open and short faults has been randomly embedded in the op-amp. Twenty three faults were embedded in 3 bit ADC and ten faults were embedded in 3 bit DAC.

A technique integrating the oscillation, power supply current and I/sub DDQ/ based testing of circuit under test (CUT) is presented. A CMOS operational amplifier with floating gate input transistors, designed for operation at /spl plusmn/2.5 V in 1.5 /spl mu/m n-well CMOS process, is used as the CUT. The faults simulating possible short and open manufacturing defects are introduced using the fault injection transistors. The change in oscillation frequency, power supply current and quiescent current is observed for fault detection. Two op-amps have been designed, one with twenty two short faults and the other with a combination of five open and seven short faults. Twenty two short faults and twelve combined open and short faults (except two short faults) have been detected by the combined testing methodology.

Phase noise is the major cause of performance degradation in OFDM systems. Hot carriers (HCs), found in the CMOS-based synchronization circuits, are high-mobility charge carriers that affect the MOSFETs' stability by increasing the required operating threshold voltages. The HC effect manifests itself as the phase noise, which increases with the continued MOSFET operation and results in the performance degradation of the voltage-controlled oscillator (VCO) built on the MOSFETs. The MOSFET instability impacts on the OFDM system performance, by inducing intercarrier interference (ICI) and common phase error (CPE) on the subcarriers. In this paper, we evaluate the effect of ICI self-cancellation coding on the phase noise induced by the hot-carrier effect in OFDM systems.

In this paper, a low-power (/spl plusmn/0.4V) operational amplifier is designed in a standard CMOS process. The amplifier has a dc gain of 7000 (77 dB), and bandwidth 30 kHz. The design incorporates a low voltage current mirror with a forward bias between source and substrate of the MOSFET to reduce the threshold voltage.

In designing ALUs, many techniques have been followed. The functional units of an ALU have been realized using conventional transistors and pass transistor gates. In this paper, we present the design of a 4 bit ALU using multi-input floating gate (MIFG) CMOS reconfigurable logic. It has been designed in a 1.5 /spl mu/m technology for 3 V operation. The ALU can perform four arithmetic and four logical operations. The core of the ALU, which is a full adder circuit, has been realized using MIFG transistors. Additional logic gates have also been built using MIFG transistors. The design we present is simple in structure with significantly lesser number of transistors and interconnections when compared to earlier designs.

This paper presents an effective built-in current sensor (BICS), which has a very small impact on the performance of the circuit under test (CUT). The proposed BICS works in two-modes the normal mode and the test mode. In the normal mode, the BICS is isolated from the CUT due to which there is no performance degradation of the CUT. In the testing mode, our BICS detects the abnormal current caused by permanent manufacturing defects. Furthermore, our BICS can also distinguish the type of defect induced (gate-source short, source-drain short and drain-gate short). Our BICS requires neither an external voltage source nor current source. Hence the BICS requires less area and is more efficient than the conventional current sensors. The circuit under test is a 10-bit digital-to-analog converter using charge-scaling architecture.

The present work involves integration of the simulation stage of design of a VLSI circuit chip and its testing stage. SPICE simulator, TEK LV511 ASIC design verification system and TekWAVES, a test program generator for LV511 were integrated. A software interface, in C language, has been developed between SPICE and the testing tools (TekWAVES and LV511). The functionality of the software interface developed is multifold. It takes input from either SPICE 2G.6 or SPICE 3E.1. The output generated by the software interface can be given as input to either TekWAVES or LV511. A graphical user interface has also been developed with OPENWINDOWS using XView toolkit on SUN workstation. The software interface could be easily linked with VLSI design tools such as MAGIC layout editor. >

The present work reports the design, implementation and testing of readout interface electronic circuits using switched-capacitor and ring oscillator techniques in 2/spl mu/m n-well CMOS technology. For MOS C-V type sensors, the switched capacitor technique is more appropriate for relatively small capacitance change compared to the ring oscillator technique which suits mostly for large capacitance variation. It is shown that the switched-capacitor readout interface circuit can be used to measure sensor capacitance change with high resolution and is insensitive to parasitic capacitances.