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A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium–zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8- \mu \textm CAAC-IGZO/0.18- \mu \textm CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV. [ABSTRACT FROM AUTHOR]

Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V. [ABSTRACT FROM AUTHOR]

A boosting pass gate (BPG) suitable for a programmable routing switch including a $c$ -axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-state current and a storage capacitor. This OS BPG achieves a routing switch with fewer transistors than a conventional routing switch having a combination of a PG and an static RAM (SRAM) cell. Owing to the boosting effect, the switching characteristics, at not only positive transition but also negative transition of input signals, of the OS BPG are improved without using overdriving. In circuits fabricated with a hybrid process of a CMOSFET and a CAAC-IGZO FET with gate lengths of 0.5 and 1.0 $\mu $ m, the net delays of the OS BPG, 75 and 58 ns, at driving voltages of 2.0 and 2.5 V have been found to be less than those of the conventional routing switch (SRAM-based PG, SRAM PG) by about 79% and 62%, respectively. It has also been confirmed that a field-programmable gate array (FPGA) chip utilizing the OS BPG as a routing switch reduces the layout areas of routing switches and the whole chip by 61% and 22%, respectively, and increases the maximum operating frequencies at driving voltage of 2.0 and 2.5 V by about 2.8 times and 1.6 times of those of the FPGA chip utilizing the SRAM PG as a routing switch. [ABSTRACT FROM PUBLISHER]