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Virtual platforms provide a full hardware/software platform to study device limitations in an early stages of the design flow and to develop software without requiring a physical implementation. This paper describes the development process of a virtual platform for Deep Packet Inspection (DPI) hardware accelerators by using Transaction Level Modeling (TLM). We propose two DPI architectures oriented to System-on-Chip FPGA. The first architecture, CPU-DMA based architecture, is a hybrid CPU/FPGA where the packets are filtered in the software domain. The second architecture, Hardware-IP based architecture, is mainly implemented in the hardware domain. We have created two virtual platforms and performed the simulation, the debugging and the analysis of the hardware/software features, in order to compare results for both architectures.

Different causes of the gate leakage origin in AlGaN/GaN HEMTs on Si have been studied through numerical simulations. Based on DC measured results and employing Sentaurus Device, different trap effects under the Schottky gate must be included to reproduce the measured transfer characteristics in subthreshold regime. Additionally, numerical simulation aspects for GaN-based HEMTs are also detailed.

This paper describes the work done to design a SoC platform for real-time on-line pattern search in TCP packets for Deep Packet Inspection (DPI) applications. The platform is based on a Xilinx Zynq programmable SoC and includes an accelerator that implements a pattern search engine that extends the original Boyer-Moore algorithm with timing and logical rules, that produces a very complex set of rules. Also, the platform implements different modes of operation, including SIMD and MISD parallelism, which can be configured on-line. The platform is scalable depending of the analysis requirement up to 8 Gbps. High-Level synthesis and platform based design methodologies have been used to reduce the time to market of the completed system.

DC characteristics of AlGaN/GaN on Si MOS-HEMTs are measured and numerically simulated, with substrate temperature up to 140°C, varying the gate width and gate length. Different gate recess depths are simulated in ATLAS in order to further investigate and optimize the device performance. Thermal boundary conditions and device thermal resistance are included in the structure for accurate simulation of the heating response. In addition, the relationship of the threshold voltage and saturation velocity with the substrate temperature and gate width has been studied and set in order to ease the modelling of these devices.

Availability of hardware implementations of super-resolution image reconstruction algorithms is limited mostly by their logical and memory requirements. This is also the case for other image processing algorithms such as hyperspectral, image compression, image coding, video coding. In previous publications we have introduced a new execution flow that tackles the problem of high memory requirements of a restoration-interpolation super-resolution kernel by carrying out processing in a macroblock-by-macroblock manner. In this work we present the modelling framework used for the evaluation of the proposed execution flow. The modelling process is presented in a step-by-step manner by means of a real-life example of implementation of super-resolution image reconstruction with description of the choices made at every stage and explanation of the reasoning behind. In the presented case the use of the proposed frame-work led to a hardware implementation with real-time capabilities. This frame-work can be applied to similar algorithms, helping system designers in achieving better work organization and efficiency.

AlGaN/GaN HEMTs with sapphire substrate have been measured and numerically simulated considering self-heating effects. A complete DC performance was realized to extract the main electrical parameters with the aim to obtain a proper characterization of the sample. Afterwards, an accuracy and simple methodology has been established to determine the device thermal resistance with other possible substrates, Si, SiC and Mo, which are more suitable due to their lower thermal conductivity. Finally, we modify a compact model for AlGaN/GaN transistors to include the extrinsic resistances obtained from numerical simulations with all substrates.

In this work, the factors of reduction of memory requirements and increase in memory traffic associated with the change from reference frame level (baseline algorithm) to macroblock-level for the Super-Resolution (SR) image restoration non-uniform grid projection algorithm are compared over combinations of algorithm parameter values. Then, based on the results of a study on the share of algorithm steps code in the total requirements, the code with larger room for optimization has been identified and optimized. The introduction of a new addressing scheme that takes advantage of the algorithms static characteristics have led to a state in which for 87 out of 96 tested combinations (QCIF frame format) the factor of memory occupancy reduction is greater than the factor of increase in memory trafile. This result opens a way for efficient hardware implementations.

This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high-level synthesis methodology to RTL micro architecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The FPGA implementation is capable to run at 100 MHz, and macro blocks are processed in 6, 500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the tasks for frame generation and visualization on a TFT screen. The FPGA implements both the DF core and a General Purpose Memory Controller (GPMC) slave core. Both cores are connected to the PowerPC440 embedded processor using Local Link interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device. An ASIC implementation of the deblocking filter has been done using UMC CMOS 65nm technology. The ASIC implementation is running at 181.8 MHz, occupying an area of 596, 392.4 μm2.

High dynamic range displays based on dual panel LCD are a viable option for building a low-cost solution for providing high bit depth visualization systems. One of the factors limiting the usability of this type of displays are the computation requirements of the algorithm necessary for correct visualization using the two stacked panels. In this work we present the methodology and the results of mapping this algorithm on a CPU+GPU platform using the OpenCL 1.1 API. Visualization of a 2048×2048 image when executed on a CPU+GPU (AMD Radeon V7800) platform is performed up to 7.6 times faster then when only the CPU is used. The first results are promising and encourage the use of GPUs (or APUs) for acceleration of this kind of processing.

In this work we present a novel execution flow for the super-resolution image restoration (SRIR) non-uniform grid projection algorithm -- the macroblock-level flow. The novel flow is compared with the reference frame-level flow. The frame-level flow is characterized by the fact that transitions from one step of the algorithm to another occur only after the current step is carried out for all macro blocks (MBs) of the frame being currently processed. The novel flow carries out complete processing of one MB before the processing of another MB starts. The memory requirements of both schemes are evaluated in detail and compared. The study on the achievable memory reduction in total memory requirements was carried out for different values of the algorithm parameters: the MB size, scale factor, search area size and number of reference frames included in the sliding frame window. The results show quantitatively that the parameter that influences storage instantiation the most and has the greatest influence on the total memory size is the number of reference frames in the sliding frame window. The conducted study shows that, for a QCIF frame format, switching from frame-to macroblock-level is feasible and fully validated functionally and that the new execution flow can lead to memory reduction by a factor of 6.8 to 40, depending on the algorithm parameters values. Memory reduction greatly facilitates hardware implementations of the algorithm and this is the main result claimed. But the reduction in memory size comes at the cost of increasing the number of memory accesses and therefore communications traffic. The increase noted in memory accesses it to be quantified in future work as well as the potential impact on power consumption. The reduction in memory size might also make it fit on chip without turning to external memory, thereby reducing power consumption. This trade off in power is yet to be quantified.

In this paper, we present the strategy for evaluating the performance of a variety of configurations of an architecture template for a computer vision system (CVS). For this study a generic model of an architecture is used to address the modular design of the CVS. This modular nature approach could be used to build a more complex system by integrating several applications which perform different kind of data processing issues but sharing a common architecture. In our current work, a visual tracking system with real-time behaviour (25 frames/sec) is modelled and mapped on the model of a pipelined multiprocessor platform. The tracking system performance and shared resource usage were analyzed to determine the real architecture capacity and also to find out possible bottlenecks in order to propose new solutions which allow more applications to be mapped on the platform template in the future.

This paper presents VIPACES (Verification Interface Primitives for the development of AXI Compliant Elements and Systems), a simple environment for the verification of AMBA 3 AXI systems in Verification IP (VIP) production. The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.

This contribution reports our research in developing an integrated inductor library. From a tutorial perspective the main limitations of this element, when grown on standard silicon technologies, are presented, offering measured results taken from a set of fabricated inductors and design guidelines to improve their performance. The modeling aspects are also covered, we present results for different equivalent lumped circuits and parameter extraction styles. From the designer's point of view, we state the main characteristics that a good integrated inductor library should include. We also report our proposed solution for this task consisting in a set of tools to automate the element selection such as their laying-out. This library development procedure and the associated tools cover the lack of these elements in present offered design kits.

This paper presents an approach to improve the quality of digital images over the sensor resolution using superresolution techniques. In order to obtain a feasible low cost implementation, the resources have been restricted to those that can be found in a generic video encoder, i.e.: the motion estimator, the motion compensator, image loop memory, etc. The super-resolution system has been implemented over a codesign platform developed by the Philips Research Laboratories in Eindhoven, while performing minimal changes on the overall hardware architecture. Nevertheless, this methodology can easily be extended to any generic video encoder architecture. The results show important improvements in the image quality, assuming that sufficient sample data is available. Based on these results, some generalizations can be made about the impact of the sampling process on the quality of the super-resolution image.

This paper describes the work in progress of the European IST-2001-34410 CAMELLIA project, which focuses on a platform-based development of a smart imaging core to be embedded in smart cameras. Therefore the work within the CAMELLIA project comprises the specification and implementation of smart imaging applications including the development of required new algorithms and hardware. Based on an existing video encoding architecture for MPEG-4 Simple Profile, the aim is to design a smart imaging core, which is suitable for automotive and mobile communication applications. Thereby the encoding architecture is to be extended with processing units for low- and mid-level smart imaging functions. To indicate the applicability of this platform-based development, a first approach for a motion estimation based background detection using a hardware motion estimation unit is illustrated in this paper. Furthermore, first results employing the background detection to detect moving objects in video sequences using a functional simulator of a video encoding architecture are presented.

A gallium arsenide automated layout generation system (OLYMPO) for VLSI circuits and system design has been developed. Cell, macrocell and module compilers are the basis of the layout automation tool. The cell and macrocell compiler takes a circuit schematic at logic level and outputs a mask layout. The compiler uses a full-custom layout style, called RN-based cell model. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator for module generation. Experimental results for datapath generation (adders, multipliers, FIR filters, register modules, among others) demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.

The paper reports on design decisions taken in the modelling, design and implementation of a full set of SPARC v8 Integer Unit versions and gives data about the experimental results obtained. VHDL was the description language, Synopsys tools were for the logical synthesis, and Duet Technologies' Epoch was used for the physical layout of the final circuits. These have been carried out in a 0.35 /spl mu/m, three-metal layer CMOS process. The description strategy and the design flow methodology allow us to obtain quantitative results that characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. This design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.