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Decoupling capacitors are required for power integrity performance. The use of package landside capacitors (LSCs) and/or board backside decoupling imposes significant design constraints on achievable system height. Low realizable capacitance due to limited component area and the need for additional package edge pins are also common design challenges on single-sided devices. On the other hand, due to surface-mount technology yield concern mobile platforms are usually voided on board surface copper layer to safeguard designs from interaction with LSCs causing waste of board resource. This paper presents a new decoupling capacitor technology which enhances capacitor effectiveness enabling single-sided board designs at competitive form factor and reduced system cost. Up to 70% capacitor cost saving and $\sim$16 mm$^{2}$ area shrink are shown feasible in addition to jitter reduction and battery life improvements.

Package design rules are traditionally determined by signal integrity reasons. However, these determine the total package inductance and the number of capacitors that can be installed, in turn determining the highest frequency impedance peak in the power delivery network. This paper provides an overview of design rule impact to electrical metrics. Simple equations and simulations based on electromagnetic extractions of representative microprocessor packages are utilized throughout. Based on these guidelines are provided for capacitor spacing and PTH size & placement evaluation as logic block sizes shrink with process node advancement.

High current voltage regulators for microelectronic loads like microprocessors and field programmable gate arrays have stringent overshoot requirements due to reliability and performance implications. Toward this end this paper presents two novel inductor energy reduction schemes for overshoot mitigation. In first scheme inductor energy is transferred to load capacitance in a physically adjacent domain via an inter-domain switch. Results show a 40% reduction in overshoot magnitude. The second scheme eliminates inductor energy increase via a fast duty ratio clamp resulting in 22% overshoot reduction. Both schemes save overall system power - the former via energy transfer and the latter via reduction in energy build up, thereby making them superior to conventional methods. Salient equations describing overshoot behavior, and simulation results of mitigation mechanisms for multi-domain scenarios are provided.

Merger of multiple loads on single voltage rail results in increase in self and coupling noise due to close proximity of load spatial distribution and limited package resources for individual isolation inductor. This paper presents a new filtering technique to mitigate self and cross-noise concerns on multiple closely spaced cascaded loads via positive and/or negative coupled inductors and carefully designed coupling polarities. Analytical descriptions and detailed evaluations for two and three load systems are discussed. Transient and frequency domain simulation results validate the theory showing up to 67% noise mitigation. In addition, approximately 3X area reduction is shown to be feasible. Design guidelines are derived to decide choice of mutual inductance and coupling polarities to maximize design benefits.

With modern low power circuits needing supply voltages around 0.6 [V], there is a growing need for accurately accounting for DC variations. To accentuate the problem proliferation of power supplies for extended battery life has forced tightly co-located voltage regulators which can easily see 20–50 [mV] variation on common ground plane. Independent analysis of loads therefore can lead to suboptimal power and performance estimates. This paper presents analysis and design methodology to study DC interaction of input and output network for power converters to accurately account for spatial distribution of current and the resulting potential differences. The contribution also enables important design aspects such as sense point optimization and PCB & package layout bottleneck identification. Paper documents design of a 1 [V] output buck voltage regulator with 4% output voltage spread for illustration.

Placement of discrete capacitors per unit area is restricted by solder resist opening (SRO) spacing rule. In addition to processor die size and bump pitch reduction over generations, number of voltage rail increase due to power management requirements have led to insufficient independent capacitors allowed for each load for self and cross-noise mitigations [1-4]. This paper presents a new capacitor technology to eliminate need of SRO spacing for performance and/or area benefits. Up to 30% impedance reduction and 38% increase in total capacitance per unit area is shown to be feasible. In addition, integration of isolation filter for cross-noise mitigations is described. Design guidelines are derived to decide integrated negative coupling factor for optimized self and cross-noise reduction.

This paper presents design considerations for grouping multiple loads to a common power plane. Power management & VR low load efficiency are covered briefly. The main focus is power integrity aspects to address differing load excitations, noise sensitivities, and wide spatial distribution. Design guidelines are illustrated with an example supported by simulation and experimental data.

This paper presents analysis & methodology for impedance design of distributed voltage domains supplied from high frequency voltage regulators (VRs). The approach addresses entire system including the combination of routing parasitics, decoupling capacitor dynamics, and control design for a low impedance solution. The detailed modeling is applicable to any power converter — on die, on package, power management IC (PMIC) & mother board VRs, where control bandwidth, decoupling capacitor & power delivery network (PDN) resonances, and load transients are in a narrow frequency range.

Integrated voltage regulators (IVRs) are central to Intel microprocessor power delivery since the Fourth Generation Core™ products with advantages of lower board cost and area, distributed power management, higher dynamic power, and smaller package size. This paper focusses on IVR generated voltage ripple distinguishing it from a lumped element design for a low frequency discrete component voltage regulator (VR), and emphasizing combined power conversion and power integrity (PI) analysis including package parasitics, spatial distribution of loads, inductor implementation, and capacitance. The voltage ripple reduces effective minimum voltage for computational logic and increases jitter for analog circuits. It is shown that detailed accurate modeling and combined PI and power conversion techniques are essential for analysis and design.

All IoT systems require multiple sensors to collect environment information via analog to digital convertor (ADC). In several medical applications and industrial instrumentation, signals need to be captured with high resolution therefore the ADC requires an extremely quiet reference. This paper presents modeling and physical design considerations for a 12-bit ADC reference voltage supply to meet a 244 μV noise target. A fully differential approach is used in the electromagnetic and circuit modeling to capture noise on all parts of the passive network. Noise quantification accuracy is studied for different analyses that are part of the design flow: FEA, macro-modeling & SPICE simulation. Noise reduction in physical design through PVT invariant band gap and electromagnetic isolation through Faraday cage are investigated.

The focus of this paper is power integrity design for noise sensitive circuits in the context of integrated voltage regulators (IVRs). Analysis and design require a combination of traditional noise mitigation and power conversion techniques simultaneously accounting for distributed load, parasitics, and decoupling, and IVR control mechanisms. Both passive and active techniques are described to target noise components based on the electrical proximity to their source and the intervening IVR controls. Simulation results are used to illustrate the concepts and effectiveness of design options.

Microprocessors and FPGAs need to enable simpler and compact platforms via integration of self-contained test and training circuits, training of data interface buffers for process and temperature variation being a prime example. This paper studies package embedding of resistors for buffer tuning and presents a scheme to utilize a single resistor to train a large number of buffers without increase in latency. Using SNR analysis, transient noise simulations and the consequent filtering latencies it is shown that embedding the compensation resistor on the package reduces the calibration time by 5µs while also reducing the filter size by a factor of 10.

This paper analyses use of solid metal fill between BGA balls or LGA pins of packages, and between die bumps. The basic principle is to benefit from higher metal-density per unit volume of the substrate in the current path to deliver enhanced electrical, thermal and mechanical performance. Paper conceptualizes different structures and simulated data is presented to show case benefits. Results show power delivery impedance peak reduction by 10 % in the 100 kHz-10 MHz range. In addition, package inductor benefit of 40 % lower DC resistance is reported.

Gated power delivery network (PDN) system design requires careful decoupling capacitor allocation between ungated and gated loads. This paper illustrates the pros and cons of ungated and gated capacitors to system performance based on impedance and latency characterization. Solution with only ungated decoupling gives power benefits whereas gated decoupling provides optimized performance but larger latency. Simulations of microprocessor packages are used to illustrate challenges and decision factors.

Minimizing power supply voltage noise is critical for high performance microprocessors. This paper uses time domain analysis to explore dependencies between design parameters, voltage response and impedance profile for ramp type loads that are common to compute logic blocks. It is shown that the conventional impedance profile based design is not sufficient. In addition the analysis clarifies non-intuitive behaviors of the voltage response, and leads to guidelines for design space exploration.

Noise coupling between different circuits powered by a single voltage regulator needs to be mitigated for functionality and performance targets like speed and jitter. This paper presents the idea of using negatively coupled inductors to suppress noise coupled between loads. Mathematical description of a simple two load case is used to illustrate efficacy and derive design guidelines. Circuit topologies with principles to generate minimal realizations for arbitrary number of loads are explained. Transient and frequency domain simulation results validate the theory presented showing up to 75% coupled noise mitigation and 30% overall noise reduction. Passive structures for realization on standard printed circuit board and substrate technology are included along with sample 3D-extraction results to establish their applicability.

Optimal power performance balance is critical for high performance microprocessors. This paper addresses different microprocessor power gating architectures and their impact to power performance trade-offs considering AC and DC metrics. It is shown that package resource allocation is critical to ensuring effectiveness of expensive die capacitance used for mitigating voltage droop. Power delivery impedance including the effect of power gating architecture and package resources is analyzed in detail to provide design guidelines. Experimental data from Intel® VI generation Core™ processor is presented for validation.

Optimal power delivery network design relies on decoupling capacitors that consume significant package and board real estate, which is becoming scarce due to shrinking chip sizes and overall system form factors. This paper addresses noise reduction via capacitor interconnection between different voltage domains to leverage decoupling capacitors across domains. Novel structures that integrate decoupling and interconnection capacitor are then proposed. The complete solution delivers more than 40% noise reduction per unit capacitor area. Simulation results are provided for illustration.

As traditional relational database have limitation of scalability in the respect of data as well as number of clients. Column oriented databases overcome this problem with the cost of lacking transaction features as compared to relational database. Column oriented databases only assure single row atomic transaction and does not support Snapshot Isolation. In this paper we show how atomicity in multi-row transaction and snapshot isolation can be achieved for column oriented database using RDMBS.

The analysis of the effect of dead time in a PWM inverter is important to realize its impact on the low frequency harmonics in the inverter and for appropriate dead time compensator design. This paper analyzes the dead-time effect in space-vector PWM (SVM) inverters considering various SVM schemes that include some non-conventional SVMs and even hybrid SVMs. Also, the effect of the current zero-crossing zone in applications with large current ripple is considered in the analysis and it has been found that this inclusion is important. Experimental results are presented that agree with the analysis.

The dual-active-bridge (DAB) topology is ideally suited for high-power dc-dc conversion, especially when bidirectional power transfer is required. However, it has the drawback of high circulating currents and hard switching at light loads, if wide variation in input and output is expected. To address these issues, this paper presents a comprehensive analysis and experimental results with pulsewidth-modulation (PWM) control of the DAB. The PWM control is in addition to phase-shift modulation between the two H-bridges. The analysis addresses PWM of one bridge at a time and of both bridges simultaneously. In the latter, five distinct modes arise based on the choice of PWM and load condition. The possibilities are analyzed for optimizing power density and efficiency for low-load operation. Finally, a composite scheme combining single and dual PWM is proposed that extends the soft-switching range down to zero-load condition, reduces rms and peak currents, and results in significant size reduction of the transformer. Experimental results are presented with a 10-kW prototype.

This paper presents the development of a high-power high-voltage and high-frequency capacitor charger. A four element resonant converter that operates as a frequency controlled current source is utilized. The converter has zero-voltage switching for the primary side MOSFETs, zero-current switching for the output fast recovery rectifier diodes, and utilizes parasitics in the circuits. Basic operation of the circuit is presented followed by detailed implementation aspects - converter, power components, control, and thermal design. Experimental results obtained from testing of the fabricated prototype are presented.

In this paper, we propose an improved average dynamic model for a single phase one quadrant unity power factor rectifier (UPFR). The new model is motivated by unsatisfactory experimental results using control strategies that were developed using a previously available model. Based on the new model, an adaptive control strategy is designed. Experimental results are obtained and compared with a digital redesign of the standard cascaded linear controller. Comparison shows a better steady state performance for the nonlinear controller while the linear strategy is seen to have a faster dynamic response.

In this paper, we present a digital implementation of a single quadrant one phase unity power factor (UPF) rectifier based on a nonlinear control strategy. In a previous paper, the authors designed an adaptive control strategy to show asymptotic (exponential) stability for the phase current and output voltage tracking errors. Here, the result is first implemented in Simulink via a discrete controller acting on a continuous average model of the UPF rectifier. With a sufficiently high sampling frequency, the transient and steady state performance achieved with the continuous control strategy is reproduced. Next, we present experimental results when the controller is implemented with a rapid prototyping kit. Experimental results show low THD and near unity power factor for the input current, and excellent transient response for the output voltage. Details of the experimental setup are also provided.

This paper presents full and reduced order observation strategies for a subclass of systems that are bilinear in the immeasurable states. Lyapunov analysis is carried out to derive the conditions for convergence of the observed states for all strategies. The full order observer is then utilized in the problem of bus voltage regulation effected by a STATCOM acting as a controlled reactive current source. Simulations results are presented to show efficacy of the observation strategy integrated with the nonlinear STATCOM controller with regard to bus voltage regulation in the presence of disturbances in load and uncertainty in system frequency.

This paper presents a strategy for controlling a STATCOM to act as an instantaneous reactive current source. The STATCOM, consisting of a three phase inverter along with a capacitive filter for the dc bus and inductive line-side filters, is modeled with the overall objective of using it for load voltage regulation. Fast control of the reactive current is achieved using direct feedback linearization with respect to one control input. The other control input is used to indirectly regulate the dc bus capacitor voltage via regulation of the real current to a quasi-steady state value. Asymptotic stability of the system is rigorously established and a region of convergence is computed as a by-product of the stability analysis. Simulation results of the controlled STATCOM integrated with a distribution system model and a load voltage controller show the efficacy of the control strategy.

This paper presents a comparison of linear and nonlinear control strategies for a STATCOM to act as an instantaneous reactive current source. The STATCOM is modeled as a three phase inverter along with a DC bus and inductive line-side filters. The dynamic response of the DC bus voltage is limited by the allowable magnitude of charging and discharging currents inside the STATCOM. The linear controller proposed is designed using LQR for the small-signal STATCOM model. The nonlinear controller is designed using a Lyapunov based strategy. Large signal analysis is presented for the nonlinear controller to show exponential regulation of the system states. Simulation results of the controlled STATCOM integrated with a distribution system model compare performance of the controllers designed.

This work presents a novel lithium-ion battery charger based on pulse charging technique. A central power supply acting as a controlled current source is sequentially connected in parallel with different batteries through an array of switches. A forward converter realizes the controlled current source. Magnetics are restricted to the inductor and transformer of the forward converter. Each battery contains plurality of Li-ion cells, the number being determined by the voltage level of the application. The switch array at the output provides charging and discharging pulses to individual cells. Charging algorithm expected to increase the lifetime and performance of Li-ion cells along with charge balancing for applications involving series string of Li-ion cells is presented. Simulation results to demonstrate the proposed methodology are presented.

In this paper, new stator pole tip geometry has been investigated. The new stator pole tip and conventional stator pole tip SRM are analyzed using finite element analysis (FEA). It is observed that a small change in stator pole tip geometry results in a significant change in the characteristics of motor. The new stator pole tip results in more flux linkages and hence more saturation of motor at same current. The new pole tip is further analyzed by constructing 5 designs of the SRM with different pole tip parameters and doing a single phase and two-phase FEA analysis. It is observed that with certain pole tip parameters, the single phase torque has a smooth profile. Using the FEA data, torque profile for two phase operation of motor, is generated for the above 5 designs. Minimum torque ripple obtained for all the designs are compared. It is observed that by choosing the stator pole tip parameter properly, the torque ripple can be optimized for a particular motor operation

Dynamic modeling of switched reluctance motors (SRMs) is usually done on a per phase basis. However, in most applications, SRMs are used with simultaneous excitation of more than one phase. Thus, a model accounting for mutual coupling in the presence of magnetic saturation is needed to predict and optimize their performance in terms of efficiency and torque ripple. This paper presents a two phase excitation model of the SRM. Motor symmetry is used to reduce the amount of flux linkage data needed for the model. An experimental procedure to obtain the flux linkage data is described. Measured flux linkage data for the 8/6 SRM are included. Simulation results obtained from the two phase model implemented in Simulink are presented along with their implications for steady state performance.

Fast voltage regulation using static compensators requires a dynamic system model that is valid on an instantaneous basis. This paper presents a general modeling strategy that allows design of fast voltage regulation controller while accounting for system parameters. The co-ordinate transform used to model the system facilitates extraction of linearized system dynamics with the help of circuit simulators. It is shown that the problem of voltage regulation using instantaneous reactive current is non-minimum phase for certain operating conditions, thereby limiting achievable dynamic response irrespective of the control design method. Simulation results with a controller designed using input output bode plots are presented to illustrate efficacy of the proposed method.

In this paper, a nonlinear control strategy is designed for a single quadrant unity power factor rectifier. Asymptotic (exponential) stability is demonstrated via a Lyapunov stability argument.

This paper presents a novel power distribution system for supplying multiple individually regulated outputs from a central power supply acting as a controlled current source that contains all the magnetic components. The individual output voltages are filtered by means of capacitors. The current source is realized with a buck converter. The outputs are connected to the current source on a time-shared basis and regulated individually by constant frequency PWM. The buck converter is controlled using average current control. Simulation results and experimental results from a laboratory prototype are presented.

This paper presents a novel power distribution system for supplying multiple individually regulated outputs from a current source that contains all the magnetic components. Realization of the current source with buck, buck-boost, and SEPIC converters is discussed. Individual outputs are regulated by hysteretic control while the converter output current is regulated using average current control. Simulation results for the system using a SEPIC converter as a current source are presented.