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In this paper, finite element modeling is performed to investigate the mechanisms ofreliability performance for wafer level packages (WLP) compared to chip scale ball grid array (BGA) packagesunder impact or drop loading conditions. Several scenarios are defined to reveal the different mechanisms of dynamic performance in WLP and BGA packages. Global/local finite element modeling is performed with the use of the direct acceleration input (DAI) method. In the first scenario of the simulation, a WLP (ball on I/O) package is compared to a BGA package with same ball geometries when package size is fixed. The vertical compliance at the package corner balls in BGA, due to the corner ball attachment to the compliant substrate/mold compound, makes BGA producing significantly less stresses than in WLP. However, when considering the second scenario, in which the same die is packaged with BGA and WLP (ball on I/O), respectively, the size of the package in BGA has increased, which presents the opposite effect in reducing the solder ball drop reliability. In the third scenario, a copper post WLP package is studied. It is found that the horizontal compliance by the epoxy layer, which is used to encapsulate the copper posts, has released the stresses in solder balls greatly under impact loading. Package size, vertical local compliance in BGA, and the horizontal compliance in WLP, constitute the major factors in determining the reliability performance of final products. Therefore, in the last scenario, a same device is packaged with a copper post WLP and a BGA, respectively. It is found the drop performance of a WLP is comparable to a BGA package. Wafer level packages are demonstrated to have comparable or even better drop performance than a BGA package. Existing experimental data show excellent agreement with the findings and observations in this study.

In this paper, an integrated testing, finite element modeling and failure analysis approach for drop test reliability of wafer level packages is developed to examine the shock performance of large array wafer level packages. For standard JEDEC drop test, it has been found that corner component group (group A) failed first for 12×12 array packages. This is different from previously reported failure test data of BGA packages. Careful analysis concluded that the high failure rate of group A is mainly due to the effect of mounting screws rather than the intrinsic strength of the package. For a given WLP, corner balls always fail first during drop test. The crack initiates at inner side of the solder joint and propagate towards the opposite side. The primary failure is always on the intermetallic compound (IMC) at WLP side. It has been found that drop reliability significantly decreases with array size increasing. Novel finite element modeling approach has been developed to correlate with experimental data. The finite element model was validated with experimental board strain data, and frequency analysis. In-plane principal strain at corner locations and maximum peeling stress in IMC at critical solder joints are used to correlate with experimental data. Excellent agreement was reached to predict the failure rate of components in each group. Two new findings have been observed and validated. One is that existing JEDEC board design will lead group A components fail first for certain array size of wafer level packages. Another finding is that PCB board strain does not always correlate with maximum peeling stress in solder joints when array size changes.

Transportation systems can be represented by graphs with travel weights accorded to each of the edges that represent the roads to be travelled. This paper gives brief introduction of the Euler's path and the description of Chinese postman problem. The said problem is then extended to multi-objective problem by considering multiple weights for each edge. Finally, this paper presents an algorithm to solve this multi-objective problem and implements the same on a biobjective Chinese postman problem.

A cost-time trade-off bulk transportation problem (BTP) with the objectives to minimize the total cost and duration of the bulk transportation without according priorities to them is considered. The entire requirement of each destination is to be met from a single source only; however a source can supply to any number of destinations subject to the availability of the commodity at it. The Extremum Difference Method (EDM) is applied to obtain the set of Pareto optimal solutions of this problem. This work provides an alternate procedure to obtain the solutions obtained by Prakash et al. [9].