Search

This paper presents design and implementation of a 100-MHz Analog-to-Information Converter (AIC) based on Random Demodulator (RD); for this purpose, we used off-the-shelf components to implement the analog front-end and a SoC-FPGA chip to implement the digital hardware/software subsystem. Analog front-end is composed of one mixer and one low-pass filter, which were implemented by using a Gilbert Cell and a passive RC circuit, respectively. Hardware/software sub-system was implemented on the Field Programmable Array (FPGA) and Hard Processor System (HPS) sides of the SoC-FPGA chip, where FPGA side was used to implement the hardware that manages RD and HPS side was used to implement spectrum recovery algorithms. Finally, verification results showed that designed AIC can recover sparse signals of 100 MHz bandwidth, where a sub-Nyquist rate of 4 MHz is used along with two Compressive Sensing (CS) recovery algorithms.

This work presents hardware implementation of 4 Spectrum Sensing (SS) techniques for ATSC/A53 TV signals, defined in the IEEE 802.22 standard. The implemented techniques are: Field Sync Correlation Detector (FSCD), Segment-Sync Autocorrelation Detector (SSAD), Spectral Correlation (SC), and Pilot Sensing (PS). FSCD and SSAD use the synchronization information in the ATSC signal to measure the occupancy of the channel; and SC and PS are based on the spectral features of the ATSC signal. The 4 techniques were implemented on an FPGA and their performance was checked using an ATSC signal captured in field. Both FSCD and SSAD detect ATSC signals with Signal-to-Noise Ratios (SNRs) above −14.5 dB; SC detects ATSC signals with SNRs above −25 dB; and PS detects ATSC signals with SNRS above −33 dB.

The design of blind rendezvous strategies for dynamic spectrum access in multi-users, multi-hop networks is a challenging task. In this paper, a two radios synchronization strategy that minimizes the time to rendezvous in multi-users networks is analyze. In fact, it has been recently demonstrated that this synchronization strategy provides optimum results in terms of maximum time to rendezvous (MTTR). In this paper, the analysis to the expected time to rendezvous (ETTR) and derive analytical expressions for its numerical computation is extended. The estimated ETTR is compared with those obtained by simulation, using a representative blind rendezvous channel hopping sequence. The results indicate that the numerical expressions provide good estimates of the actual ETTR. Moreover, the ETTR achieved by the proposed synchronization strategy has proven to be bounded by the MTTR of a pair-wise rendezvous process irrespective of the number of users and the network topology. This property makes the analyzed rendezvous mechanism, and particularly the synchronization strategy, suitable for the deployment of large and dense networks.

Security is one of the possible fields in human society in which robotics can be applied. Human guards usually perform a range of tasks in which a robot can provide help. A security company collaborated with us in the design and development of a robot that should serve in patrolling large indoor areas, interacting with humans, welcoming, providing information, and be a telepresence platform for the human security guards. In this paper we present a preliminary experiment which involved this new robot in two roles: security and guidance. The former being important especially during night, and the latter being common in daytime, when guards are usually interacting with people who ask them information. The results of the experiment with 55 participants showed how the perception of the appearance of the robot and its effectiveness are influenced by its behaviour and its related perceived more authoritative or kinder traits. These results provide useful indication for the employment of robot guards in a real world situation.

In this paper we present the design, development and preliminary tests of Robotman, a robot that combines qualities for interaction with humans, and security patrolling services. The robot is inspired by the information obtained from a security company in which their personnel not only perform security patrolling services, but have to interact with people, providing additional information about the area they safeguard. The robot is able to perform security patrols during the night while functioning as a guide during the day. We designed and implemented a robust, easy to assemble, anthropomorphic security robot aiming to patrol large indoor areas, interact with humans, welcome, provide information and guide clients to their destination, as well as function as a telepresence platform for the human security guards. Our results suggest that Robotman is user friendly and pleasing to the people, it can perform security tasks and interact with them.

Attention Deficit Hyperactivity Disorder (ADHD) is a disorder that affects 1 out of 5 Colombian children, converting into a real public health problem in the country. Conventional treatments such as medication and neuropsychological therapy have been proved to be insufficient in order to decrease high incidence levels of ADHD in the principal Colombian cities. This work presents a design and development of a videogame that uses a brain computer interface not only to serve as an input device but also as a tool to monitor neurophysiologic signal. The video game named “The Harvest Challenge” puts a cultural scene of a Colombian coffee grower in its context, where a player can use his/her avatar in three mini games created in order to reinforce four fundamental aspects: i) waiting ability, ii) planning ability, iii) ability to follow instructions and iv) ability to achieve objectives. The details of this collaborative designing process of the multimedia tool according to the exact clinic necessities and the description of interaction proposals are presented through the mental stages of attention and relaxation. The final videogame is presented as a tool for sustained attention training in children with ADHD using as an action mechanism the neuromodulation of Beta and Theta waves through an electrode located in the central part of the front lobe of the brain. The processing of an electroencephalographic signal is produced automatically inside the videogame allowing to generate a report of the theta/beta ratio evolution — a biological marker, which has been demonstrated to be a sufficient measure to discriminate of children with and without deficit.

This paper presents the design and implementation of an OpenRISC-based System-on-Chip (SoC), which is composed of hardware cores implementing the Digital Signal Processing (DSP) functions: Finite Impulse Response (FIR) filter, Infinite Impulse Response (IIR) filter and Fast Fourier Transform (FFT). The FIR-filter core is based on the transpose realization form, the IIR-filter core is based on the Second Order Sections (SOS) architecture and the FFT core is based on the Radix 22 Single Delay Feedback (R22SDF) architecture. The three cores are compatible with the Wishbone SoC bus, and they were described using generic and structural VHDL. In-system hardware verification was performed by using an OpenRisc-based SoC synthesized on an Altera FPGA. Tests showed that the designed DSP cores are suitable for building SoC based on the OpenRisc processor and the Wishbone bus.

This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.

This paper presents an efficient systolic architecture for solving the Hermitian eigenvalue problem, which is a common issue in the spectrum sensing function of cognitive radio systems like WRANs. The designed architecture uses a novel upper triangular structure to improve performance with respect to the BLV array. The processing elements are based on sequential CORDIC processors to perform two complex Jacobi rotations. Tests and results show that the proposed architecture is suitable to design the spectrum sensing function of cognitive radio systems. The systolic architecture was described using generic structural VHDL and tested using an Altera FPGA.