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We present Heterogeneous Parallel Virtual Machine (HPVM), a compiler framework for hardware-agnostic programming on heterogeneous compute platforms. HPVM introduces a hardware-agnostic parallel intermediate representation with constructs for the hierarchical task, data, and pipeline parallelism, including dataflow parallelism, and supports multiple front-end languages. In addition, HPVM provides optimization passes that navigate performance, energy, and accuracy tradeoffs, and includes retargetable back ends for a wide range of diverse hardware targets, including central processing units, graphics processing units, domain-specific accelerators, and field-programmable gate arrays. Across diverse hardware platforms, HPVM optimizations provide significant performance and energy improvements, while preserving object-code portability. With these capabilities, HPVM facilitates developers, domain experts, and hardware vendors in programming modern heterogeneous systems. [ABSTRACT FROM AUTHOR]

We present Illinois Extended Reality testbed (ILLIXR), the first fully open-source XR system and research testbed. ILLIXR enables system innovations with end-to-end co-designed hardware, compiler, OS, and algorithms, and driven by end-user perceived Quality-of-Experience (QoE) metrics. Using ILLIXR, we provide the first comprehensive quantitative analysis of performance, power, and QoE for a complete XR system and its individual components. We describe several implications of our results that propel new directions in architecture, systems, and algorithms research for domain-specific systems in general, and XR in particular. [ABSTRACT FROM AUTHOR]

Recent research in disciplined shared-memory programming models presents a unique opportunity for rethinking the multicore memory hierarchy for better efficiency in terms of complexity, performance, and energy. The DeNovo hardware system showed that for deterministic programs written using such disciplined models, hardware can be much more efficient than the current state of the art. For DeNovo to be adopted by commercial systems, however, it is necessary to extend it to support nondeterministic applications as well; for example, applications using lock synchronization. This article proposes DeNovoND, a system that provides support for disciplined nondeterministic codes with locks while retaining the simplicity, performance, and energy benefits of DeNovo. The authors designed and implemented simple memory consistency semantics for safe nondeterminism using distributed queue-based locks and access signatures. The resulting protocol avoids transient states, invalidation traffic, directory sharer-lists, and false sharing, which are all significant sources of inefficiency in existing protocols. Their experiments showed that DeNovoND provides comparable or better execution time for applications designed for lock synchronization. In addition, it incurs 33 percent less network traffic on average relative to a state-of-the-art invalidation-based protocol, which directly translates into energy savings. [ABSTRACT FROM AUTHOR]

Future microprocessors need low-cost solutions for reliable operation in the presence of failure-prone devices. A promising approach is to detect hardware faults by deploying low-cost software-level symptom monitors. However, there remains a nonnegligible risk that several faults might escape these detectors to produce silent data corruptions (SDCs). Evaluating and bounding SDCs is, therefore, crucial for low-cost resiliency solutions. The authors present Relyzer, an approach that can systematically analyze all application fault sites and identify virtually all SDC-causing program locations. Instead of performing fault injections on all possible application-level fault sites, which is impractical, Relyzer carefully picks a small subset. It employs novel fault-pruning techniques that reduce the number of fault sites by either predicting their outcomes or showing them equivalent to others. Results show that 99.78 percent of faults are pruned across 12 studied workloads, reducing the complete application resiliency evaluation time by 2 to 6 orders of magnitude. Relyzer, for the first time, achieves the capability to list virtually all SDC-vulnerable program locations, which is critical in designing low-cost application-centric resiliency solutions. Relyzer also opens new avenues of research in designing error-resilient programming models as well as even faster (and simpler) evaluation methodologies. [ABSTRACT FROM PUBLISHER]

The article discusses various reports published within the issue, including one by Matthew J. Bridges on the automatic parallelization of non-numeric programs and another by Naveen Neelankantam on hardware atomicity.

Mobile devices primarily processing multimedia data need to support multimedia quality with limited battery energy. To address this challenging problem, researchers have introduced adaptation into multiple system layers, ranging from hardware to applications. Given these adaptive layers, a new challenge is how to coordinate them to fully exploit the adaptation benefits. This paper presents a novel cross-layer adaptation framework, called GRACE-1, that coordinates the adaptation of the CPU hardware, OS scheduling, and multimedia quality based on users' preferences. To balance the benefits and overhead of cross-layer adaptation, GRACE-1 takes a hierarchical approach: It globally adapts all three layers to large system changes, such as application entry or exit, and internally adapts individual layers to small changes in the processed multimedia data. We have implemented GRACE-1 on an HP laptop with the adaptive Athlon CPU, Linux-based OS, and video codecs. Our experimental results show that, compared to schemes that adapt only some layers or adapt only to large changes, GRACE-1 reduces the laptop's energy consumption up to 31.4 percent while providing better or the same video quality. [ABSTRACT FROM AUTHOR]

Reports the importance of simulation in the computer system performance in the United States. Historical background of shared-memory multiprocessors; Features of the instruction-level parallelism; Increase the read miss parallelism. INSET: Performing Valid Studies with Unvalidated Simulators..

Presents information on a study which evaluates the impact of instruction-level parallelism (LIP) on the performance of shared-memory multiprocessors. Applications using detailed simulation; Interaction between software prefetching and ILP techniques in shared-memory multiprocessors.

Presents a description of an optimization continuum with compiletime and post-runtime as endpoints and how different classes of program optimization falls within it. Differences between program optimizations done by the compiler and the architecture; Taxonomy of optimizations; Optimization systems that redefine the architecture-compiler interface. INSET: Heterogeneity in processor architectures: A new obstacle for...

Describes several models in shared memory consistency systems. Uniprocessor memory consistency; Understanding sequential consistency; Implementing sequential consistency; Relaxed memory models; Programmer-centric models.

The article discusses various reports published within the issue including one by S.K. Iyer and V.S. Borkar on the different sources of variability and errors and their trends going forward.

Discusses the Illinois project, Global Resource Adaptation through Cooperation (GRACE), which aims to develop a cross-layer adaptation framework to reduce energy while preserving desirable application quality for mobile devices running realtime multimedia applications. Common uses of adaptation techniques; Features of a cross-layer adaptive system; Hierarchical approach adopted by the GRACE project.

Reports the importance of understanding the performance of simulation tools of the computer in the United States. Exploration of design alternatives for future high-performance computers; Interaction between the process steps refines the performance model; Increase the complexity of target architectures and applications.