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The presence of sparsity in both input features and weights within convolutional neural networks offers a valuable opportunity to significantly reduce the number of computations required during inference. Moreover, the practice of compressing input data serves to diminish storage requirements and lower data transfer costs, ultimately enhancing overall power efficiency. However, the compression of randomly sparse inputs introduces challenges in the input matching process, often resulting in substantial hardware overhead and increased power consumption. These challenges arise due to the irregular nature of sparse inputs and the variability in convolutional strides. In response to these challenges, this research introduces an innovative data compression method, named Stride-Aware Sparsity Compression (StarSPA), designed to effectively locate valid input values and expedite the multiplication process. To fully capitalize on this proposed compression method, a weight-stationary approach is employed for efficient convolution. Comprehensive simulations demonstrate that the proposed accelerator achieves speedup factors of $1.17\times $ , $1.05\times $ , $1.09\times $ , $1.23\times $ , and $1.12\times $ when compared to the recent accelerator named SparTen for AlexNet, VGG16, GoogLeNet, ResNet34, and EfficientNetV2, respectively. Furthermore, FPGA implementation of the core reveals a noteworthy $2.55\times $ reduction in hardware size and a $5\times $ enhancement in energy efficiency when compared to SparTen.

The inherent sparsity present in convolutional neural networks (CNNs) offers a valuable opportunity to significantly decrease the computational workload during inference. Nevertheless, leveraging unstructured sparsity typically comes with the trade-off of increased complexity or substantial hardware overheads for accelerators. To address these challenges, this research introduces an innovative inner join aimed at effectively reducing the size and power consumption of the sparsity-handling circuit. Additionally, a novel dataflow named Channel Stacking of Sparse Tensors (CSSpa) is presented, focusing on maximizing data reuse to minimize memory accesses – an aspect that significantly contributes to overall power consumption. Through comprehensive simulations, CSSpa demonstrates a $1.6\times $ speedup and a $5.6\times $ reduction in SRAM accesses when executing inference on the ResNet50 model, compared to the existing Sparten architecture. Furthermore, the implementation results reveal a notable $2.32\times $ enhancement in hardware resource efficiency and a $3.3\times $ improvement in energy efficiency compared to Sparten.

In the modern era, artificial intelligence (AI) and deep learning (DL) seamlessly integrate into various spheres of our daily lives. These cutting-edge disciplines have given rise to numerous safety-critical applications such as autonomous driving with a paramount concern on ensuring a high promise of dependability because of the high risk of human injury in the case of malfunction. Even the dependability becomes more crucial as shrinking CMOS technology feature size enhances resilience concerns due to factors like aging. In the context of DL accelerators, which heavily rely on the efficiency and speed of computations, addressing the effects of aging is of utmost significance to ensure their optimal design and performance. This paper addresses the overarching dependability issue of advanced deep neural networks (DNN) accelerators from the aging perspective. Especially, a comprehensive survey and taxonomy of techniques used to evaluate and mitigate aging effects are introduced. We cover different aging effects like permanent faults, timing errors, and lifetime issues. We review research by the layer-wise approach and categorize several resilience classes to bring out major features. The concluding part of this review highlights the questions answered and several future research directions. This study is expected to benefit researchers in different areas of DNN deployment, especially the dependability of this emergent paradigm.

In this article, a synaptic semiconductor device and its crossbar have been demonstrated for real-time artificial intelligence (AI) applications. The proposed device is a dual gate, metal-oxide-semiconductor field-effect transistor (MOSFET) with charge trapping and de-trapping capabilities to emulate synaptic weight modulation. It achieves ultra-low energy consumption in the range few-tenth of femto-Joules and can be further reduced by adjusting device parameters. Moreover, to prove the potential of the proposed device as an analog AI accelerator, it was trained and tested for an ANN based underwater image enhancement algorithm on Underwater Image Enhancement Benchmark (UIEB) dataset. The results were compared to the state-of-arts which show that our proposed algorithm works better than most of the previous works on qualitative as well as quantitative grounds. The ultra-low energy consumption of the order of one-tenth of femto-Joules makes the proposed crossbar architecture (AI accelerator) a potential candidate for real-time data intensive AI/ML applications. [ABSTRACT FROM AUTHOR]

Recently, analog in-memory computing (IMC) systems exhibit the considerable potential to break through the inherent high computational latency and energy cost of Von Neumann’s computer architecture. However, inefficient data convertor will inhibit the performance improvement of this system. The tradeoff between different data conversion circuit technologies has turned into one of the major driving forces for the analog IMC system-level improvements. The primary contribution is in two aspects. First, this article shows a digital-to-time-to-analog converter (DTAC) with the tradeoff of latency, area, and power consumption compared to a digital-to-time converter (DTC) and digital-to-analog converter (DAC). Second, we develop an innovative reconfigurable joint-quantization nonlinear analog-to-digital convertor (JQNL-ADC) architecture with lower quantization error by merging the two paradigms of uniform input quantization and uniform output quantization. Compared to conventional DAC, DTAC can reduce power and area by $50\times $ and $3\times $ , respectively. Compared to SAR-ADC, our JQNL-ADC can reduce area and power by $1.6\times $ and $2\times $ , respectively. In an example of ReRAM-based reconfigurable function-IMC (RFIMC) macro with 256-kb memory, our design can reach 112.9 TOPS/W@8bIN-8bW-8bO under the 28-nm process conditions. [ABSTRACT FROM AUTHOR]

The raindrops on the glass will affect driving safety, such as rear-view camera, outside mirror and windshield, etc. This article proposed a robust raindrop detection using deep learning on embedded platform with AI accelerator for real-time implementation. A training model is established through a convolution neural network (CNN)-like architecture to classify the images by the vehicle camera into three classes: no rain, heavy rain, and light rain. The classification results are used to control the speed of the motor to implement an automatic wiper control system. The training model, ResNet, is used to classify the image with good tradeoff between the computational cost and accuracy. For real-time application, the camera module on the Google Coral Dev board on embedded system platform is used to test the video stream and to estimate the performance of this system. Results show that the recognition accuracy reaches 95%, and the processing speed can achieve 20 frames per second (fps) on the embedded system. [ABSTRACT FROM AUTHOR]

This paper presents a study on the applicability of using approximate multipliers to enhance the performance of the VGGNet deep learning network. Approximate multipliers are known to have reduced power, area, and delay with the cost of an inaccuracy in output. Improving the performance of the VGGNet in terms of power, area, and speed can be achieved by replacing exact multipliers with approximate multipliers as demonstrated in this paper. The simulation results show that approximate multiplication has a very little impact on the accuracy of VGGNet. However, using approximate multipliers can achieve significant performance gains. The simulation was completed using different generated error matrices that mimic the inaccuracy that approximate multipliers introduce to the data. The impact of various ranges of the mean relative error and the standard deviation was tested. The well-known data sets CIFAR-10 and CIFAR100 were used for testing the network's classification accuracy. The impact on the accuracy was assessed by simulating approximate multiplication in all the layers in the first set of tests, and in selective layers in the second set of tests. Using approximate multipliers in all the layers leads to very little impact on the network's accuracy. In addition, an alternative approach is to use a hybrid of exact and approximate multipliers. In the hybrid approach, 39.14% of the deeper layer's multiplications can be approximate while having a reduced negligible impact on the network's accuracy.